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-rw-r--r--hw/petalogix_ml605_mmu.c2
-rw-r--r--hw/petalogix_s3adsp1800_mmu.c2
-rw-r--r--hw/virtex_ml507.c2
-rw-r--r--hw/xilinx.h4
-rw-r--r--hw/xilinx_timer.c17
5 files changed, 16 insertions, 11 deletions
diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c
index bff63e3..6a7d0c0 100644
--- a/hw/petalogix_ml605_mmu.c
+++ b/hw/petalogix_ml605_mmu.c
@@ -123,7 +123,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
irq[5], 115200, serial_hds[0], DEVICE_LITTLE_ENDIAN);
/* 2 timers at irq 2 @ 100 Mhz. */
- xilinx_timer_create(TIMER_BASEADDR, irq[2], 2, 100 * 1000000);
+ xilinx_timer_create(TIMER_BASEADDR, irq[2], 0, 100 * 1000000);
/* axi ethernet and dma initialization. TODO: Dynamically connect them. */
{
diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c
index 7d83c21..2cf6882 100644
--- a/hw/petalogix_s3adsp1800_mmu.c
+++ b/hw/petalogix_s3adsp1800_mmu.c
@@ -106,7 +106,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR, irq[3]);
/* 2 timers at irq 2 @ 62 Mhz. */
- xilinx_timer_create(TIMER_BASEADDR, irq[0], 2, 62 * 1000000);
+ xilinx_timer_create(TIMER_BASEADDR, irq[0], 0, 62 * 1000000);
xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0);
microblaze_load_kernel(cpu, ddr_base, ram_size,
diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c
index cace86b..79bc0d1 100644
--- a/hw/virtex_ml507.c
+++ b/hw/virtex_ml507.c
@@ -229,7 +229,7 @@ static void virtex_init(ram_addr_t ram_size,
serial_hds[0], DEVICE_LITTLE_ENDIAN);
/* 2 timers at irq 2 @ 62 Mhz. */
- xilinx_timer_create(0x83c00000, irq[3], 2, 62 * 1000000);
+ xilinx_timer_create(0x83c00000, irq[3], 0, 62 * 1000000);
if (kernel_filename) {
uint64_t entry, low, high;
diff --git a/hw/xilinx.h b/hw/xilinx.h
index 70d15cf..97afa45 100644
--- a/hw/xilinx.h
+++ b/hw/xilinx.h
@@ -16,12 +16,12 @@ xilinx_intc_create(target_phys_addr_t base, qemu_irq irq, int kind_of_intr)
/* OPB Timer/Counter. */
static inline DeviceState *
-xilinx_timer_create(target_phys_addr_t base, qemu_irq irq, int nr, int freq)
+xilinx_timer_create(target_phys_addr_t base, qemu_irq irq, int oto, int freq)
{
DeviceState *dev;
dev = qdev_create(NULL, "xilinx,timer");
- qdev_prop_set_uint32(dev, "nr-timers", nr);
+ qdev_prop_set_uint32(dev, "one-timer-only", oto);
qdev_prop_set_uint32(dev, "frequency", freq);
qdev_init_nofail(dev);
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
diff --git a/hw/xilinx_timer.c b/hw/xilinx_timer.c
index e9fde28..72f7c0d 100644
--- a/hw/xilinx_timer.c
+++ b/hw/xilinx_timer.c
@@ -62,11 +62,16 @@ struct timerblock
SysBusDevice busdev;
MemoryRegion mmio;
qemu_irq irq;
- uint32_t nr_timers;
+ uint8_t one_timer_only;
uint32_t freq_hz;
struct xlx_timer *timers;
};
+static inline unsigned int num_timers(struct timerblock *t)
+{
+ return 2 - t->one_timer_only;
+}
+
static inline unsigned int timer_from_addr(target_phys_addr_t addr)
{
/* Timers get a 4x32bit control reg area each. */
@@ -78,7 +83,7 @@ static void timer_update_irq(struct timerblock *t)
unsigned int i, irq = 0;
uint32_t csr;
- for (i = 0; i < t->nr_timers; i++) {
+ for (i = 0; i < num_timers(t); i++) {
csr = t->timers[i].regs[R_TCSR];
irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
}
@@ -202,8 +207,8 @@ static int xilinx_timer_init(SysBusDevice *dev)
sysbus_init_irq(dev, &t->irq);
/* Init all the ptimers. */
- t->timers = g_malloc0(sizeof t->timers[0] * t->nr_timers);
- for (i = 0; i < t->nr_timers; i++) {
+ t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
+ for (i = 0; i < num_timers(t); i++) {
struct xlx_timer *xt = &t->timers[i];
xt->parent = t;
@@ -214,14 +219,14 @@ static int xilinx_timer_init(SysBusDevice *dev)
}
memory_region_init_io(&t->mmio, &timer_ops, t, "xilinx-timer",
- R_MAX * 4 * t->nr_timers);
+ R_MAX * 4 * num_timers(t));
sysbus_init_mmio(dev, &t->mmio);
return 0;
}
static Property xilinx_timer_properties[] = {
DEFINE_PROP_UINT32("frequency", struct timerblock, freq_hz, 62 * 1000000),
- DEFINE_PROP_UINT32("nr-timers", struct timerblock, nr_timers, 0),
+ DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
DEFINE_PROP_END_OF_LIST(),
};