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-rw-r--r--hw/alpha/dp264.c2
-rw-r--r--hw/hppa/machine.c2
-rw-r--r--hw/i386/pc.c3
-rw-r--r--hw/i386/pc_piix.c5
-rw-r--r--hw/ide/piix.c5
-rw-r--r--hw/ide/via.c2
-rw-r--r--hw/isa/Kconfig9
-rw-r--r--hw/isa/lpc_ich9.c3
-rw-r--r--hw/isa/piix3.c28
-rw-r--r--hw/isa/piix4.c10
-rw-r--r--hw/isa/vt82c686.c120
-rw-r--r--hw/mips/bootloader.c28
-rw-r--r--hw/mips/boston.c14
-rw-r--r--hw/mips/fuloong2e.c48
-rw-r--r--hw/mips/malta.c147
-rw-r--r--hw/ppc/Kconfig1
-rw-r--r--hw/ppc/pegasos2.c25
-rw-r--r--hw/ppc/prep.c2
-rw-r--r--hw/sparc64/sun4u.c1
-rw-r--r--hw/usb/vt82c686-uhci-pci.c4
20 files changed, 261 insertions, 198 deletions
diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c
index f4349eb..c502c8c 100644
--- a/hw/alpha/dp264.c
+++ b/hw/alpha/dp264.c
@@ -20,8 +20,6 @@
#include "qemu/datadir.h"
#include "net/net.h"
-#define MAX_IDE_BUS 2
-
static uint64_t cpu_alpha_superpage_to_phys(void *opaque, uint64_t addr)
{
if (((addr >> 41) & 3) == 2) {
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 19ea7c2..de1cc7a 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -30,8 +30,6 @@
#include "qemu/log.h"
#include "net/net.h"
-#define MAX_IDE_BUS 2
-
#define MIN_SEABIOS_HPPA_VERSION 6 /* require at least this fw version */
#define HPA_POWER_BUTTON (FIRMWARE_END - 0x10)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 3e86083..ef14da5 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -47,7 +47,6 @@
#include "multiboot.h"
#include "hw/rtc/mc146818rtc.h"
#include "hw/intc/i8259.h"
-#include "hw/dma/i8257.h"
#include "hw/timer/i8254.h"
#include "hw/input/i8042.h"
#include "hw/irq.h"
@@ -1320,8 +1319,6 @@ void pc_basic_device_init(struct PCMachineState *pcms,
pcspk_init(pcms->pcspk, isa_bus, pit);
}
- i8257_dma_init(isa_bus, 0);
-
/* Super I/O */
pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
pcms->vmport != ON_OFF_AUTO_ON);
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 0b1a79c..0ad0ed1 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -26,6 +26,7 @@
#include CONFIG_DEVICES
#include "qemu/units.h"
+#include "hw/dma/i8257.h"
#include "hw/loader.h"
#include "hw/i386/x86.h"
#include "hw/i386/pc.h"
@@ -39,6 +40,7 @@
#include "hw/usb.h"
#include "net/net.h"
#include "hw/ide/pci.h"
+#include "hw/ide/piix.h"
#include "hw/irq.h"
#include "sysemu/kvm.h"
#include "hw/kvm/clock.h"
@@ -225,6 +227,7 @@ static void pc_init1(MachineState *machine,
pci_bus = NULL;
isa_bus = isa_bus_new(NULL, get_system_memory(), system_io,
&error_abort);
+ i8257_dma_init(isa_bus, 0);
pcms->hpet_enabled = false;
}
isa_bus_irqs(isa_bus, x86ms->gsi);
@@ -257,7 +260,7 @@ static void pc_init1(MachineState *machine,
if (pcmc->pci_enabled) {
PCIDevice *dev;
- dev = pci_create_simple(pci_bus, piix3_devfn + 1, "piix3-ide");
+ dev = pci_create_simple(pci_bus, piix3_devfn + 1, TYPE_PIIX3_IDE);
pci_ide_create_devs(dev);
idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0");
idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1");
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index de1f4f0..267dbf3 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
@@ -36,6 +36,7 @@
#include "sysemu/blockdev.h"
#include "sysemu/dma.h"
+#include "hw/ide/piix.h"
#include "hw/ide/pci.h"
#include "trace.h"
@@ -202,7 +203,7 @@ static void piix3_ide_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo piix3_ide_info = {
- .name = "piix3-ide",
+ .name = TYPE_PIIX3_IDE,
.parent = TYPE_PCI_IDE,
.class_init = piix3_ide_class_init,
};
@@ -224,7 +225,7 @@ static void piix4_ide_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo piix4_ide_info = {
- .name = "piix4-ide",
+ .name = TYPE_PIIX4_IDE,
.parent = TYPE_PCI_IDE,
.class_init = piix4_ide_class_init,
};
diff --git a/hw/ide/via.c b/hw/ide/via.c
index 82def81..e1a4294 100644
--- a/hw/ide/via.c
+++ b/hw/ide/via.c
@@ -230,7 +230,7 @@ static void via_ide_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo via_ide_info = {
- .name = "via-ide",
+ .name = TYPE_VIA_IDE,
.parent = TYPE_PCI_IDE,
.class_init = via_ide_class_init,
};
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index d42143a..18b5c6b 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -33,13 +33,20 @@ config PC87312
config PIIX3
bool
+ select I8257
select ISA_BUS
config PIIX4
bool
# For historical reasons, SuperIO devices are created in the board
# for PIIX4.
+ select ACPI_PIIX4
+ select I8254
+ select I8257
+ select I8259
+ select IDE_PIIX
select ISA_BUS
+ select MC146818RTC
select USB_UHCI
config VT82C686
@@ -53,6 +60,7 @@ config VT82C686
select I8254
select I8257
select I8259
+ select IDE_VIA
select MC146818RTC
select PARALLEL
@@ -67,6 +75,7 @@ config LPC_ICH9
bool
# For historical reasons, SuperIO devices are created in the board
# for ICH9.
+ select I8257
select ISA_BUS
select ACPI_SMBUS
select ACPI_X86_ICH
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 4553b59..8694e58 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -34,6 +34,7 @@
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "qemu/range.h"
+#include "hw/dma/i8257.h"
#include "hw/isa/isa.h"
#include "migration/vmstate.h"
#include "hw/irq.h"
@@ -722,6 +723,8 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS);
isa_bus_irqs(isa_bus, lpc->gsi);
+
+ i8257_dma_init(isa_bus, 0);
}
static bool ich9_rst_cnt_needed(void *opaque)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 48f9ab1..808fd4e 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -25,12 +25,11 @@
#include "qemu/osdep.h"
#include "qemu/range.h"
#include "qapi/error.h"
+#include "hw/dma/i8257.h"
#include "hw/southbridge/piix.h"
#include "hw/irq.h"
#include "hw/isa/isa.h"
#include "hw/xen/xen.h"
-#include "sysemu/xen.h"
-#include "sysemu/reset.h"
#include "sysemu/runstate.h"
#include "migration/vmstate.h"
#include "hw/acpi/acpi_aml_interface.h"
@@ -155,9 +154,9 @@ static void piix3_write_config_xen(PCIDevice *dev,
piix3_write_config(dev, address, val, len);
}
-static void piix3_reset(void *opaque)
+static void piix3_reset(DeviceState *dev)
{
- PIIX3State *d = opaque;
+ PIIX3State *d = PIIX3_PCI_DEVICE(dev);
uint8_t *pci_conf = d->dev.config;
pci_conf[0x04] = 0x07; /* master, memory and I/O */
@@ -289,15 +288,21 @@ static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
static const MemoryRegionOps rcr_ops = {
.read = rcr_read,
.write = rcr_write,
- .endianness = DEVICE_LITTLE_ENDIAN
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
};
static void pci_piix3_realize(PCIDevice *dev, Error **errp)
{
PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+ ISABus *isa_bus;
- if (!isa_bus_new(DEVICE(d), get_system_memory(),
- pci_address_space_io(dev), errp)) {
+ isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev),
+ pci_address_space_io(dev), errp);
+ if (!isa_bus) {
return;
}
@@ -306,7 +311,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
memory_region_add_subregion_overlap(pci_address_space_io(dev),
PIIX_RCR_IOPORT, &d->rcr_mem, 1);
- qemu_register_reset(piix3_reset, d);
+ i8257_dma_init(isa_bus, 0);
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@@ -328,6 +333,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
+ dc->reset = piix3_reset;
dc->desc = "ISA bridge";
dc->vmsd = &vmstate_piix3;
dc->hotpluggable = false;
@@ -370,7 +376,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
piix3, PIIX_NUM_PIRQS);
pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
-};
+}
static void piix3_class_init(ObjectClass *klass, void *data)
{
@@ -405,7 +411,7 @@ static void piix3_xen_realize(PCIDevice *dev, Error **errp)
*/
pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
piix3, XEN_PIIX_NUM_PIRQS);
-};
+}
static void piix3_xen_class_init(ObjectClass *klass, void *data)
{
@@ -413,7 +419,7 @@ static void piix3_xen_class_init(ObjectClass *klass, void *data)
k->config_write = piix3_write_config_xen;
k->realize = piix3_xen_realize;
-};
+}
static const TypeInfo piix3_xen_info = {
.name = TYPE_PIIX3_XEN_DEVICE,
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 15f344d..8fc1db6 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -28,6 +28,7 @@
#include "hw/irq.h"
#include "hw/southbridge/piix.h"
#include "hw/pci/pci.h"
+#include "hw/ide/piix.h"
#include "hw/isa/isa.h"
#include "hw/intc/i8259.h"
#include "hw/dma/i8257.h"
@@ -139,9 +140,11 @@ static void piix4_isa_reset(DeviceState *dev)
pci_conf[0xab] = 0x00;
pci_conf[0xac] = 0x00;
pci_conf[0xae] = 0x00;
+
+ d->rcr = 0;
}
-static int piix4_ide_post_load(void *opaque, int version_id)
+static int piix4_post_load(void *opaque, int version_id)
{
PIIX4State *s = opaque;
@@ -156,7 +159,7 @@ static const VMStateDescription vmstate_piix4 = {
.name = "PIIX4",
.version_id = 3,
.minimum_version_id = 2,
- .post_load = piix4_ide_post_load,
+ .post_load = piix4_post_load,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(dev, PIIX4State),
VMSTATE_UINT8_V(rcr, PIIX4State, 3),
@@ -254,7 +257,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) {
return;
}
- pci_ide_create_devs(PCI_DEVICE(&s->ide));
/* USB */
qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2);
@@ -277,7 +279,7 @@ static void piix4_init(Object *obj)
PIIX4State *s = PIIX4_PCI_DEVICE(obj);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
- object_initialize_child(obj, "ide", &s->ide, "piix4-ide");
+ object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE);
object_initialize_child(obj, "uhci", &s->uhci, "piix4-usb-uhci");
object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM);
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 8f65625..3f9bd0c 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -17,11 +17,13 @@
#include "hw/isa/vt82c686.h"
#include "hw/pci/pci.h"
#include "hw/qdev-properties.h"
+#include "hw/ide/pci.h"
#include "hw/isa/isa.h"
#include "hw/isa/superio.h"
#include "hw/intc/i8259.h"
#include "hw/irq.h"
#include "hw/dma/i8257.h"
+#include "hw/usb/hcd-uhci.h"
#include "hw/timer/i8254.h"
#include "hw/rtc/mc146818rtc.h"
#include "migration/vmstate.h"
@@ -248,6 +250,8 @@ static const ViaPMInitInfo vt82c686b_pm_init_info = {
.device_id = PCI_DEVICE_ID_VIA_82C686B_PM,
};
+#define TYPE_VT82C686B_PM "vt82c686b-pm"
+
static const TypeInfo vt82c686b_pm_info = {
.name = TYPE_VT82C686B_PM,
.parent = TYPE_VIA_PM,
@@ -259,6 +263,8 @@ static const ViaPMInitInfo vt8231_pm_init_info = {
.device_id = PCI_DEVICE_ID_VIA_8231_PM,
};
+#define TYPE_VT8231_PM "vt8231-pm"
+
static const TypeInfo vt8231_pm_info = {
.name = TYPE_VT8231_PM,
.parent = TYPE_VIA_PM,
@@ -543,8 +549,13 @@ struct ViaISAState {
PCIDevice dev;
qemu_irq cpu_intr;
qemu_irq *isa_irqs;
- ISABus *isa_bus;
- ViaSuperIOState *via_sio;
+ ViaSuperIOState via_sio;
+ RTCState rtc;
+ PCIIDEState ide;
+ UHCIState uhci[2];
+ ViaPMState pm;
+ PCIDevice ac97;
+ PCIDevice mc97;
};
static const VMStateDescription vmstate_via = {
@@ -557,10 +568,23 @@ static const VMStateDescription vmstate_via = {
}
};
+static void via_isa_init(Object *obj)
+{
+ ViaISAState *s = VIA_ISA(obj);
+
+ object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
+ object_initialize_child(obj, "ide", &s->ide, TYPE_VIA_IDE);
+ object_initialize_child(obj, "uhci1", &s->uhci[0], TYPE_VT82C686B_USB_UHCI);
+ object_initialize_child(obj, "uhci2", &s->uhci[1], TYPE_VT82C686B_USB_UHCI);
+ object_initialize_child(obj, "ac97", &s->ac97, TYPE_VIA_AC97);
+ object_initialize_child(obj, "mc97", &s->mc97, TYPE_VIA_MC97);
+}
+
static const TypeInfo via_isa_info = {
.name = TYPE_VIA_ISA,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(ViaISAState),
+ .instance_init = via_isa_init,
.abstract = true,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
@@ -584,24 +608,74 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
{
ViaISAState *s = VIA_ISA(d);
DeviceState *dev = DEVICE(d);
+ PCIBus *pci_bus = pci_get_bus(d);
qemu_irq *isa_irq;
+ ISABus *isa_bus;
int i;
qdev_init_gpio_out(dev, &s->cpu_intr, 1);
isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1);
- s->isa_bus = isa_bus_new(dev, get_system_memory(), pci_address_space_io(d),
- &error_fatal);
- s->isa_irqs = i8259_init(s->isa_bus, *isa_irq);
- isa_bus_irqs(s->isa_bus, s->isa_irqs);
- i8254_pit_init(s->isa_bus, 0x40, 0, NULL);
- i8257_dma_init(s->isa_bus, 0);
- mc146818_rtc_init(s->isa_bus, 2000, NULL);
+ isa_bus = isa_bus_new(dev, pci_address_space(d), pci_address_space_io(d),
+ errp);
+
+ if (!isa_bus) {
+ return;
+ }
+
+ s->isa_irqs = i8259_init(isa_bus, *isa_irq);
+ isa_bus_irqs(isa_bus, s->isa_irqs);
+ i8254_pit_init(isa_bus, 0x40, 0, NULL);
+ i8257_dma_init(isa_bus, 0);
+
+ /* RTC */
+ qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
+ if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
+ return;
+ }
+ isa_connect_gpio_out(ISA_DEVICE(&s->rtc), 0, s->rtc.isairq);
for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
if (i < PCI_COMMAND || i >= PCI_REVISION_ID) {
d->wmask[i] = 0;
}
}
+
+ /* Super I/O */
+ if (!qdev_realize(DEVICE(&s->via_sio), BUS(isa_bus), errp)) {
+ return;
+ }
+
+ /* Function 1: IDE */
+ qdev_prop_set_int32(DEVICE(&s->ide), "addr", d->devfn + 1);
+ if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) {
+ return;
+ }
+
+ /* Functions 2-3: USB Ports */
+ for (i = 0; i < ARRAY_SIZE(s->uhci); i++) {
+ qdev_prop_set_int32(DEVICE(&s->uhci[i]), "addr", d->devfn + 2 + i);
+ if (!qdev_realize(DEVICE(&s->uhci[i]), BUS(pci_bus), errp)) {
+ return;
+ }
+ }
+
+ /* Function 4: Power Management */
+ qdev_prop_set_int32(DEVICE(&s->pm), "addr", d->devfn + 4);
+ if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) {
+ return;
+ }
+
+ /* Function 5: AC97 Audio */
+ qdev_prop_set_int32(DEVICE(&s->ac97), "addr", d->devfn + 5);
+ if (!qdev_realize(DEVICE(&s->ac97), BUS(pci_bus), errp)) {
+ return;
+ }
+
+ /* Function 6: MC97 Modem */
+ qdev_prop_set_int32(DEVICE(&s->mc97), "addr", d->devfn + 6);
+ if (!qdev_realize(DEVICE(&s->mc97), BUS(pci_bus), errp)) {
+ return;
+ }
}
/* TYPE_VT82C686B_ISA */
@@ -615,7 +689,7 @@ static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
pci_default_write_config(d, addr, val, len);
if (addr == 0x85) {
/* BIT(1): enable or disable superio config io ports */
- via_superio_io_enable(s->via_sio, val & BIT(1));
+ via_superio_io_enable(&s->via_sio, val & BIT(1));
}
}
@@ -639,13 +713,12 @@ static void vt82c686b_isa_reset(DeviceState *dev)
pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
}
-static void vt82c686b_realize(PCIDevice *d, Error **errp)
+static void vt82c686b_init(Object *obj)
{
- ViaISAState *s = VIA_ISA(d);
+ ViaISAState *s = VIA_ISA(obj);
- via_isa_realize(d, errp);
- s->via_sio = VIA_SUPERIO(isa_create_simple(s->isa_bus,
- TYPE_VT82C686B_SUPERIO));
+ object_initialize_child(obj, "sio", &s->via_sio, TYPE_VT82C686B_SUPERIO);
+ object_initialize_child(obj, "pm", &s->pm, TYPE_VT82C686B_PM);
}
static void vt82c686b_class_init(ObjectClass *klass, void *data)
@@ -653,7 +726,7 @@ static void vt82c686b_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- k->realize = vt82c686b_realize;
+ k->realize = via_isa_realize;
k->config_write = vt82c686b_write_config;
k->vendor_id = PCI_VENDOR_ID_VIA;
k->device_id = PCI_DEVICE_ID_VIA_82C686B_ISA;
@@ -670,6 +743,7 @@ static const TypeInfo vt82c686b_isa_info = {
.name = TYPE_VT82C686B_ISA,
.parent = TYPE_VIA_ISA,
.instance_size = sizeof(ViaISAState),
+ .instance_init = vt82c686b_init,
.class_init = vt82c686b_class_init,
};
@@ -684,7 +758,7 @@ static void vt8231_write_config(PCIDevice *d, uint32_t addr,
pci_default_write_config(d, addr, val, len);
if (addr == 0x50) {
/* BIT(2): enable or disable superio config io ports */
- via_superio_io_enable(s->via_sio, val & BIT(2));
+ via_superio_io_enable(&s->via_sio, val & BIT(2));
}
}
@@ -703,13 +777,12 @@ static void vt8231_isa_reset(DeviceState *dev)
pci_conf[0x6b] = 0x01; /* Fast IR I/O Base */
}
-static void vt8231_realize(PCIDevice *d, Error **errp)
+static void vt8231_init(Object *obj)
{
- ViaISAState *s = VIA_ISA(d);
+ ViaISAState *s = VIA_ISA(obj);
- via_isa_realize(d, errp);
- s->via_sio = VIA_SUPERIO(isa_create_simple(s->isa_bus,
- TYPE_VT8231_SUPERIO));
+ object_initialize_child(obj, "sio", &s->via_sio, TYPE_VT8231_SUPERIO);
+ object_initialize_child(obj, "pm", &s->pm, TYPE_VT8231_PM);
}
static void vt8231_class_init(ObjectClass *klass, void *data)
@@ -717,7 +790,7 @@ static void vt8231_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- k->realize = vt8231_realize;
+ k->realize = via_isa_realize;
k->config_write = vt8231_write_config;
k->vendor_id = PCI_VENDOR_ID_VIA;
k->device_id = PCI_DEVICE_ID_VIA_8231_ISA;
@@ -734,6 +807,7 @@ static const TypeInfo vt8231_isa_info = {
.name = TYPE_VT8231_ISA,
.parent = TYPE_VIA_ISA,
.instance_size = sizeof(ViaISAState),
+ .instance_init = vt8231_init,
.class_init = vt8231_class_init,
};
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 99991f8..f5f42f2 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -165,15 +165,29 @@ void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr)
bl_gen_nop(p); /* delay slot */
}
-void bl_gen_jump_kernel(uint32_t **p, target_ulong sp, target_ulong a0,
- target_ulong a1, target_ulong a2, target_ulong a3,
+void bl_gen_jump_kernel(uint32_t **p,
+ bool set_sp, target_ulong sp,
+ bool set_a0, target_ulong a0,
+ bool set_a1, target_ulong a1,
+ bool set_a2, target_ulong a2,
+ bool set_a3, target_ulong a3,
target_ulong kernel_addr)
{
- bl_gen_load_ulong(p, BL_REG_SP, sp);
- bl_gen_load_ulong(p, BL_REG_A0, a0);
- bl_gen_load_ulong(p, BL_REG_A1, a1);
- bl_gen_load_ulong(p, BL_REG_A2, a2);
- bl_gen_load_ulong(p, BL_REG_A3, a3);
+ if (set_sp) {
+ bl_gen_load_ulong(p, BL_REG_SP, sp);
+ }
+ if (set_a0) {
+ bl_gen_load_ulong(p, BL_REG_A0, a0);
+ }
+ if (set_a1) {
+ bl_gen_load_ulong(p, BL_REG_A1, a1);
+ }
+ if (set_a2) {
+ bl_gen_load_ulong(p, BL_REG_A2, a2);
+ }
+ if (set_a3) {
+ bl_gen_load_ulong(p, BL_REG_A3, a3);
+ }
bl_gen_jump_to(p, kernel_addr);
}
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index cab63f4..edda87e 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -352,7 +352,10 @@ static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr)
* a2/$6 = 0
* a3/$7 = 0
*/
- bl_gen_jump_kernel(&p, 0, (int32_t)-2, fdt_addr, 0, 0, kernel_entry);
+ bl_gen_jump_kernel(&p,
+ true, 0, true, (int32_t)-2,
+ true, fdt_addr, true, 0, true, 0,
+ kernel_entry);
}
static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
@@ -425,7 +428,7 @@ static inline XilinxPCIEHost *
xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,
hwaddr cfg_base, uint64_t cfg_size,
hwaddr mmio_base, uint64_t mmio_size,
- qemu_irq irq, bool link_up)
+ qemu_irq irq)
{
DeviceState *dev;
MemoryRegion *cfg, *mmio;
@@ -437,7 +440,6 @@ xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,
qdev_prop_set_uint64(dev, "cfg_size", cfg_size);
qdev_prop_set_uint64(dev, "mmio_base", mmio_base);
qdev_prop_set_uint64(dev, "mmio_size", mmio_size);
- qdev_prop_set_bit(dev, "link_up", link_up);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@@ -730,21 +732,21 @@ static void boston_mach_init(MachineState *machine)
boston_memmap[BOSTON_PCIE0].size,
boston_memmap[BOSTON_PCIE0_MMIO].base,
boston_memmap[BOSTON_PCIE0_MMIO].size,
- get_cps_irq(&s->cps, 2), false);
+ get_cps_irq(&s->cps, 2));
xilinx_pcie_init(sys_mem, 1,
boston_memmap[BOSTON_PCIE1].base,
boston_memmap[BOSTON_PCIE1].size,
boston_memmap[BOSTON_PCIE1_MMIO].base,
boston_memmap[BOSTON_PCIE1_MMIO].size,
- get_cps_irq(&s->cps, 1), false);
+ get_cps_irq(&s->cps, 1));
pcie2 = xilinx_pcie_init(sys_mem, 2,
boston_memmap[BOSTON_PCIE2].base,
boston_memmap[BOSTON_PCIE2].size,
boston_memmap[BOSTON_PCIE2_MMIO].base,
boston_memmap[BOSTON_PCIE2_MMIO].size,
- get_cps_irq(&s->cps, 0), true);
+ get_cps_irq(&s->cps, 0));
platreg = g_new(MemoryRegion, 1);
memory_region_init_io(platreg, NULL, &boston_platreg_ops, s,
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 5ee546f..34befa5 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -49,7 +49,6 @@
/* Fuloong 2e has a 512k flash: Winbond W39L040AP70Z */
#define BIOS_SIZE (512 * KiB)
-#define MAX_IDE_BUS 2
/*
* PMON is not part of qemu and released with BSD license, anyone
@@ -180,8 +179,12 @@ static void write_bootloader(CPUMIPSState *env, uint8_t *base,
/* Second part of the bootloader */
p = (uint32_t *)(base + 0x040);
- bl_gen_jump_kernel(&p, ENVP_VADDR - 64, 2, ENVP_VADDR, ENVP_VADDR + 8,
- loaderparams.ram_size, kernel_addr);
+ bl_gen_jump_kernel(&p,
+ true, ENVP_VADDR - 64,
+ true, 2, true, ENVP_VADDR,
+ true, ENVP_VADDR + 8,
+ true, loaderparams.ram_size,
+ kernel_addr);
}
static void main_cpu_reset(void *opaque)
@@ -196,29 +199,6 @@ static void main_cpu_reset(void *opaque)
}
}
-static void vt82c686b_southbridge_init(PCIBus *pci_bus, int slot, qemu_irq intc,
- I2CBus **i2c_bus)
-{
- PCIDevice *dev;
-
- dev = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(slot, 0), true,
- TYPE_VT82C686B_ISA);
- qdev_connect_gpio_out(DEVICE(dev), 0, intc);
-
- dev = pci_create_simple(pci_bus, PCI_DEVFN(slot, 1), "via-ide");
- pci_ide_create_devs(dev);
-
- pci_create_simple(pci_bus, PCI_DEVFN(slot, 2), "vt82c686b-usb-uhci");
- pci_create_simple(pci_bus, PCI_DEVFN(slot, 3), "vt82c686b-usb-uhci");
-
- dev = pci_create_simple(pci_bus, PCI_DEVFN(slot, 4), TYPE_VT82C686B_PM);
- *i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c"));
-
- /* Audio support */
- pci_create_simple(pci_bus, PCI_DEVFN(slot, 5), TYPE_VIA_AC97);
- pci_create_simple(pci_bus, PCI_DEVFN(slot, 6), TYPE_VIA_MC97);
-}
-
/* Network support */
static void network_init(PCIBus *pci_bus)
{
@@ -315,8 +295,20 @@ static void mips_fuloong2e_init(MachineState *machine)
pci_bus = bonito_init((qemu_irq *)&(env->irq[2]));
/* South bridge -> IP5 */
- vt82c686b_southbridge_init(pci_bus, FULOONG2E_VIA_SLOT, env->irq[5],
- &smbus);
+ pci_dev = pci_create_simple_multifunction(pci_bus,
+ PCI_DEVFN(FULOONG2E_VIA_SLOT, 0),
+ true, TYPE_VT82C686B_ISA);
+ object_property_add_alias(OBJECT(machine), "rtc-time",
+ object_resolve_path_component(OBJECT(pci_dev),
+ "rtc"),
+ "date");
+ qdev_connect_gpio_out(DEVICE(pci_dev), 0, env->irq[5]);
+
+ dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide"));
+ pci_ide_create_devs(PCI_DEVICE(dev));
+
+ dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "pm"));
+ smbus = I2C_BUS(qdev_get_child_bus(dev, "i2c"));
/* GPU */
if (vga_interface_type != VGA_NONE) {
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 7c3ad09..c0a2e0a 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -36,11 +36,12 @@
#include "hw/i2c/smbus_eeprom.h"
#include "hw/block/flash.h"
#include "hw/mips/mips.h"
+#include "hw/mips/bootloader.h"
#include "hw/mips/cpudevs.h"
#include "hw/pci/pci.h"
#include "qemu/log.h"
#include "hw/mips/bios.h"
-#include "hw/ide.h"
+#include "hw/ide/pci.h"
#include "hw/irq.h"
#include "hw/loader.h"
#include "elf.h"
@@ -70,8 +71,6 @@
#define FLASH_SIZE 0x400000
-#define MAX_IDE_BUS 2
-
typedef struct {
MemoryRegion iomem;
MemoryRegion iomem_lo; /* 0 - 0x900 */
@@ -867,88 +866,63 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
/* Second part of the bootloader */
p = (uint32_t *) (base + 0x580);
- if (semihosting_get_argc()) {
- /* Preserve a0 content as arguments have been passed */
- stl_p(p++, 0x00000000); /* nop */
- } else {
- stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */
- }
-
- /* lui sp, high(ENVP_VADDR) */
- stl_p(p++, 0x3c1d0000 | (((ENVP_VADDR - 64) >> 16) & 0xffff));
- /* ori sp, sp, low(ENVP_VADDR) */
- stl_p(p++, 0x37bd0000 | ((ENVP_VADDR - 64) & 0xffff));
- /* lui a1, high(ENVP_VADDR) */
- stl_p(p++, 0x3c050000 | ((ENVP_VADDR >> 16) & 0xffff));
- /* ori a1, a1, low(ENVP_VADDR) */
- stl_p(p++, 0x34a50000 | (ENVP_VADDR & 0xffff));
- /* lui a2, high(ENVP_VADDR + 8) */
- stl_p(p++, 0x3c060000 | (((ENVP_VADDR + 8) >> 16) & 0xffff));
- /* ori a2, a2, low(ENVP_VADDR + 8) */
- stl_p(p++, 0x34c60000 | ((ENVP_VADDR + 8) & 0xffff));
- /* lui a3, high(ram_low_size) */
- stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
- /* ori a3, a3, low(ram_low_size) */
- stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
-
- /* Load BAR registers as done by YAMON */
- stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
-
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c08df00); /* lui t0, 0xdf00 */
-#else
- stl_p(p++, 0x340800df); /* ori t0, r0, 0x00df */
-#endif
- stl_p(p++, 0xad280068); /* sw t0, 0x0068(t1) */
-
- stl_p(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
-
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c08c000); /* lui t0, 0xc000 */
-#else
- stl_p(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
-#endif
- stl_p(p++, 0xad280048); /* sw t0, 0x0048(t1) */
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c084000); /* lui t0, 0x4000 */
-#else
- stl_p(p++, 0x34080040); /* ori t0, r0, 0x0040 */
-#endif
- stl_p(p++, 0xad280050); /* sw t0, 0x0050(t1) */
-
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c088000); /* lui t0, 0x8000 */
-#else
- stl_p(p++, 0x34080080); /* ori t0, r0, 0x0080 */
-#endif
- stl_p(p++, 0xad280058); /* sw t0, 0x0058(t1) */
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c083f00); /* lui t0, 0x3f00 */
-#else
- stl_p(p++, 0x3408003f); /* ori t0, r0, 0x003f */
-#endif
- stl_p(p++, 0xad280060); /* sw t0, 0x0060(t1) */
+ /*
+ * Load BAR registers as done by YAMON:
+ *
+ * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
+ * - set up PCI0 MEM0 at 0x10000000, size 0x7e00000
+ * - set up PCI0 MEM1 at 0x18200000, size 0xbc00000
+ *
+ */
+ /* Bus endianess is always reversed */
#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c08c100); /* lui t0, 0xc100 */
+#define cpu_to_gt32 cpu_to_le32
#else
- stl_p(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
+#define cpu_to_gt32 cpu_to_be32
#endif
- stl_p(p++, 0xad280080); /* sw t0, 0x0080(t1) */
-#if TARGET_BIG_ENDIAN
- stl_p(p++, 0x3c085e00); /* lui t0, 0x5e00 */
-#else
- stl_p(p++, 0x3408005e); /* ori t0, r0, 0x005e */
-#endif
- stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */
- /* Jump to kernel code */
- stl_p(p++, 0x3c1f0000 |
- ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
- stl_p(p++, 0x37ff0000 |
- (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
- stl_p(p++, 0x03e00009); /* jalr ra */
- stl_p(p++, 0x00000000); /* nop */
+ /* move GT64120 registers from 0x14000000 to 0x1be00000 */
+ bl_gen_write_u32(&p, /* GT_ISD */
+ cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
+ cpu_to_gt32(0x1be00000 << 3));
+
+ /* setup MEM-to-PCI0 mapping */
+ /* setup PCI0 io window to 0x18000000-0x181fffff */
+ bl_gen_write_u32(&p, /* GT_PCI0IOLD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
+ cpu_to_gt32(0x18000000 << 3));
+ bl_gen_write_u32(&p, /* GT_PCI0IOHD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
+ cpu_to_gt32(0x08000000 << 3));
+ /* setup PCI0 mem windows */
+ bl_gen_write_u32(&p, /* GT_PCI0M0LD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
+ cpu_to_gt32(0x10000000 << 3));
+ bl_gen_write_u32(&p, /* GT_PCI0M0HD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
+ cpu_to_gt32(0x07e00000 << 3));
+
+ bl_gen_write_u32(&p, /* GT_PCI0M1LD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
+ cpu_to_gt32(0x18200000 << 3));
+ bl_gen_write_u32(&p, /* GT_PCI0M1HD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
+ cpu_to_gt32(0x0bc00000 << 3));
+
+#undef cpu_to_gt32
+
+ bl_gen_jump_kernel(&p,
+ true, ENVP_VADDR - 64,
+ /*
+ * If semihosting is used, arguments have already been
+ * passed, so we preserve $a0.
+ */
+ !semihosting_get_argc(), 2,
+ true, ENVP_VADDR,
+ true, ENVP_VADDR + 8,
+ true, loaderparams.ram_low_size,
+ kernel_entry);
/* YAMON subroutines */
p = (uint32_t *) (base + 0x800);
@@ -1266,7 +1240,6 @@ void mips_malta_init(MachineState *machine)
MaltaState *s;
PCIDevice *piix4;
DeviceState *dev;
- DeviceState *pm_dev;
s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA));
sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);
@@ -1430,15 +1403,17 @@ void mips_malta_init(MachineState *machine)
/* Southbridge */
piix4 = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true,
TYPE_PIIX4_PCI_DEVICE);
- dev = DEVICE(piix4);
- isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
- pm_dev = DEVICE(object_resolve_path_component(OBJECT(dev), "pm"));
- smbus = I2C_BUS(qdev_get_child_bus(pm_dev, "i2c"));
+ isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0"));
+
+ dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide"));
+ pci_ide_create_devs(PCI_DEVICE(dev));
/* Interrupt controller */
- qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
+ qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq);
/* generate SPD EEPROM data */
+ dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm"));
+ smbus = I2C_BUS(qdev_get_child_bus(dev, "i2c"));
generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size);
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 769a1ea..b8d2522 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -74,7 +74,6 @@ config PEGASOS2
imply ATI_VGA
select MV64361
select VT82C686
- select IDE_VIA
select SMBUS_EEPROM
select VOF
# This should come with VT82C686
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index bb4d008..f46d4bf 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos2.c
@@ -102,7 +102,7 @@ static void pegasos2_init(MachineState *machine)
CPUPPCState *env;
MemoryRegion *rom = g_new(MemoryRegion, 1);
PCIBus *pci_bus;
- PCIDevice *dev;
+ PCIDevice *dev, *via;
I2CBus *i2c_bus;
const char *fwname = machine->firmware ?: PROM_FILENAME;
char *filename;
@@ -159,30 +159,23 @@ static void pegasos2_init(MachineState *machine)
pci_bus = mv64361_get_pci_bus(pm->mv, 1);
/* VIA VT8231 South Bridge (multifunction PCI device) */
- /* VT8231 function 0: PCI-to-ISA Bridge */
- dev = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), true,
+ via = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), true,
TYPE_VT8231_ISA);
- qdev_connect_gpio_out(DEVICE(dev), 0,
+ object_property_add_alias(OBJECT(machine), "rtc-time",
+ object_resolve_path_component(OBJECT(via),
+ "rtc"),
+ "date");
+ qdev_connect_gpio_out(DEVICE(via), 0,
qdev_get_gpio_in_named(pm->mv, "gpp", 31));
- /* VT8231 function 1: IDE Controller */
- dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 1), "via-ide");
+ dev = PCI_DEVICE(object_resolve_path_component(OBJECT(via), "ide"));
pci_ide_create_devs(dev);
- /* VT8231 function 2-3: USB Ports */
- pci_create_simple(pci_bus, PCI_DEVFN(12, 2), "vt82c686b-usb-uhci");
- pci_create_simple(pci_bus, PCI_DEVFN(12, 3), "vt82c686b-usb-uhci");
-
- /* VT8231 function 4: Power Management Controller */
- dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 4), TYPE_VT8231_PM);
+ dev = PCI_DEVICE(object_resolve_path_component(OBJECT(via), "pm"));
i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c"));
spd_data = spd_data_generate(DDR, machine->ram_size);
smbus_eeprom_init_one(i2c_bus, 0x57, spd_data);
- /* VT8231 function 5-6: AC97 Audio & Modem */
- pci_create_simple(pci_bus, PCI_DEVFN(12, 5), TYPE_VIA_AC97);
- pci_create_simple(pci_bus, PCI_DEVFN(12, 6), TYPE_VIA_MC97);
-
/* other PC hardware */
pci_vga_init(pci_bus);
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index f08714f..fcbe4c5 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -50,8 +50,6 @@
/* SMP is not enabled, for now */
#define MAX_CPUS 1
-#define MAX_IDE_BUS 2
-
#define CFG_ADDR 0xf0000510
#define KERNEL_LOAD_ADDR 0x01000000
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index 0e27715..387181f 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -66,7 +66,6 @@
#define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
#define PROM_FILENAME "openbios-sparc64"
#define NVRAM_SIZE 0x2000
-#define MAX_IDE_BUS 2
#define BIOS_CFG_IOPORT 0x510
#define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
#define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
diff --git a/hw/usb/vt82c686-uhci-pci.c b/hw/usb/vt82c686-uhci-pci.c
index 0bf2b72..46a901f 100644
--- a/hw/usb/vt82c686-uhci-pci.c
+++ b/hw/usb/vt82c686-uhci-pci.c
@@ -31,7 +31,7 @@ static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp)
static UHCIInfo uhci_info[] = {
{
- .name = "vt82c686b-usb-uhci",
+ .name = TYPE_VT82C686B_USB_UHCI,
.vendor_id = PCI_VENDOR_ID_VIA,
.device_id = PCI_DEVICE_ID_VIA_UHCI,
.revision = 0x01,
@@ -45,7 +45,7 @@ static UHCIInfo uhci_info[] = {
static const TypeInfo vt82c686b_usb_uhci_type_info = {
.parent = TYPE_UHCI,
- .name = "vt82c686b-usb-uhci",
+ .name = TYPE_VT82C686B_USB_UHCI,
.class_init = uhci_data_class_init,
.class_data = uhci_info,
};
generated by cgit v1.1 at 2024-10-21 18:33:47 +0000