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-rw-r--r--hw/riscv/boot.c62
-rw-r--r--hw/riscv/microchip_pfsoc.c7
-rw-r--r--hw/riscv/opentitan.c80
-rw-r--r--hw/riscv/sifive_u.c8
-rw-r--r--hw/riscv/spike.c25
-rw-r--r--hw/riscv/virt.c476
6 files changed, 355 insertions, 303 deletions
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 2594276..c7e0e50 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -249,29 +249,64 @@ void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
}
}
-uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
+/*
+ * This function makes an assumption that the DRAM interval
+ * 'dram_base' + 'dram_size' is contiguous.
+ *
+ * Considering that 'dram_end' is the lowest value between
+ * the end of the DRAM block and MachineState->ram_size, the
+ * FDT location will vary according to 'dram_base':
+ *
+ * - if 'dram_base' is less that 3072 MiB, the FDT will be
+ * put at the lowest value between 3072 MiB and 'dram_end';
+ *
+ * - if 'dram_base' is higher than 3072 MiB, the FDT will be
+ * put at 'dram_end'.
+ *
+ * The FDT is fdt_packed() during the calculation.
+ */
+uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
+ MachineState *ms)
{
- uint64_t temp, fdt_addr;
- hwaddr dram_end = dram_base + mem_size;
- int ret, fdtsize = fdt_totalsize(fdt);
+ int ret = fdt_pack(ms->fdt);
+ hwaddr dram_end, temp;
+ int fdtsize;
+ /* Should only fail if we've built a corrupted tree */
+ g_assert(ret == 0);
+
+ fdtsize = fdt_totalsize(ms->fdt);
if (fdtsize <= 0) {
error_report("invalid device-tree");
exit(1);
}
/*
+ * A dram_size == 0, usually from a MemMapEntry[].size element,
+ * means that the DRAM block goes all the way to ms->ram_size.
+ */
+ dram_end = dram_base;
+ dram_end += dram_size ? MIN(ms->ram_size, dram_size) : ms->ram_size;
+
+ /*
* We should put fdt as far as possible to avoid kernel/initrd overwriting
* its content. But it should be addressable by 32 bit system as well.
* Thus, put it at an 2MB aligned address that less than fdt size from the
* end of dram or 3GB whichever is lesser.
*/
temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
- fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
- ret = fdt_pack(fdt);
- /* Should only fail if we've built a corrupted tree */
- g_assert(ret == 0);
+ return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
+}
+
+/*
+ * 'fdt_addr' is received as hwaddr because boards might put
+ * the FDT beyond 32-bit addressing boundary.
+ */
+void riscv_load_fdt(hwaddr fdt_addr, void *fdt)
+{
+ uint32_t fdtsize = fdt_totalsize(fdt);
+
/* copy in the device tree */
qemu_fdt_dumpdtb(fdt, fdtsize);
@@ -279,8 +314,6 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
&address_space_memory);
qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize));
-
- return fdt_addr;
}
void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
@@ -356,6 +389,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */
}
+ if (!harts->harts[0].cfg.ext_icsr) {
+ /*
+ * The Zicsr extension has been disabled, so let's ensure we don't
+ * run the CSR instruction. Let's fill the address with a non
+ * compressed nop.
+ */
+ reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */
+ }
+
/* copy in the reset vector in little_endian byte order */
for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
reset_vec[i] = cpu_to_le32(reset_vec[i]);
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 82ae5e7..2b91e49 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -641,8 +641,11 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
}
/* Compute the fdt load address in dram */
- fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
- machine->ram_size, machine->fdt);
+ fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
+ memmap[MICROCHIP_PFSOC_DRAM_LO].size,
+ machine);
+ riscv_load_fdt(fdt_load_addr, machine->fdt);
+
/* Load the reset vector */
riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 64d5d43..353f030 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -31,47 +31,47 @@
/*
* This version of the OpenTitan machine currently supports
* OpenTitan RTL version:
- * <lowRISC/opentitan@d072ac505f82152678d6e04be95c72b728a347b8>
+ * <lowRISC/opentitan@565e4af39760a123c59a184aa2f5812a961fde47>
*
* MMIO mapping as per (specified commit):
* lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
*/
static const MemMapEntry ibex_memmap[] = {
- [IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
- [IBEX_DEV_RAM] = { 0x10000000, 0x20000 },
- [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 },
- [IBEX_DEV_UART] = { 0x40000000, 0x1000 },
- [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 },
- [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x1000 },
- [IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
- [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
- [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
- [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
- [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x1000 },
- [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x1000 },
- [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x1000 },
- [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x1000 },
- [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 },
- [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
- [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
- [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
- [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
- [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x1000 },
- [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x1000 },
- [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
- [IBEX_DEV_AES] = { 0x41100000, 0x1000 },
- [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
- [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
- [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 },
- [IBEX_DEV_KEYMGR] = { 0x41140000, 0x1000 },
- [IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 },
- [IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 },
- [IBEX_DEV_EDNO] = { 0x41170000, 0x1000 },
- [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
- [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
- [IBEX_DEV_PERI] = { 0x411f0000, 0x10000 },
- [IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 },
- [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
+ [IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
+ [IBEX_DEV_RAM] = { 0x10000000, 0x20000 },
+ [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 },
+ [IBEX_DEV_UART] = { 0x40000000, 0x40 },
+ [IBEX_DEV_GPIO] = { 0x40040000, 0x40 },
+ [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x2000 },
+ [IBEX_DEV_I2C] = { 0x40080000, 0x80 },
+ [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x40 },
+ [IBEX_DEV_TIMER] = { 0x40100000, 0x200 },
+ [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x2000 },
+ [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x100 },
+ [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x800 },
+ [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x40 },
+ [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x40 },
+ [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 },
+ [IBEX_DEV_PWRMGR] = { 0x40400000, 0x80 },
+ [IBEX_DEV_RSTMGR] = { 0x40410000, 0x80 },
+ [IBEX_DEV_CLKMGR] = { 0x40420000, 0x80 },
+ [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
+ [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x40 },
+ [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x40 },
+ [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x200 },
+ [IBEX_DEV_AES] = { 0x41100000, 0x100 },
+ [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
+ [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
+ [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 },
+ [IBEX_DEV_KEYMGR] = { 0x41140000, 0x100 },
+ [IBEX_DEV_CSRNG] = { 0x41150000, 0x80 },
+ [IBEX_DEV_ENTROPY] = { 0x41160000, 0x100 },
+ [IBEX_DEV_EDNO] = { 0x41170000, 0x80 },
+ [IBEX_DEV_EDN1] = { 0x41180000, 0x80 },
+ [IBEX_DEV_SRAM_CTRL] = { 0x411c0000, 0x20 },
+ [IBEX_DEV_IBEX_CFG] = { 0x411f0000, 0x100 },
+ [IBEX_DEV_PLIC] = { 0x48000000, 0x8000000 },
+ [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
};
static void opentitan_board_init(MachineState *machine)
@@ -294,12 +294,12 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
- create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
- memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
+ create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl",
+ memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size);
create_unimplemented_device("riscv.lowrisc.ibex.otbn",
memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
- create_unimplemented_device("riscv.lowrisc.ibex.peri",
- memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
+ create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg",
+ memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size);
}
static Property lowrisc_ibex_soc_props[] = {
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 2fb6ee2..d3ab7a9 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -616,9 +616,11 @@ static void sifive_u_machine_init(MachineState *machine)
kernel_entry = 0;
}
- /* Compute the fdt load address in dram */
- fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
- machine->ram_size, machine->fdt);
+ fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base,
+ memmap[SIFIVE_U_DEV_DRAM].size,
+ machine);
+ riscv_load_fdt(fdt_load_addr, machine->fdt);
+
if (!riscv_is_32bit(&s->soc.u_cpus)) {
start_addr_hi32 = (uint64_t)start_addr >> 32;
}
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index badc11e..cc3f6da 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -56,7 +56,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
uint64_t addr, size;
unsigned long clint_addr;
int cpu, socket;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
uint32_t *clint_cells;
uint32_t cpu_phandle, intc_phandle, phandle = 1;
char *name, *mem_name, *clint_name, *clust_name;
@@ -65,7 +65,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
"sifive,clint0", "riscv,clint0"
};
- fdt = mc->fdt = create_device_tree(&fdt_size);
+ fdt = ms->fdt = create_device_tree(&fdt_size);
if (!fdt) {
error_report("create_device_tree() failed");
exit(1);
@@ -96,7 +96,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
- for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+ for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) {
clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
qemu_fdt_add_subnode(fdt, clust_name);
@@ -121,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
s->soc[socket].hartid_base + cpu);
qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
- riscv_socket_fdt_write_id(mc, cpu_name, socket);
+ riscv_socket_fdt_write_id(ms, cpu_name, socket);
qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
@@ -147,14 +147,14 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
g_free(cpu_name);
}
- addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
- size = riscv_socket_mem_size(mc, socket);
+ addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, socket);
+ size = riscv_socket_mem_size(ms, socket);
mem_name = g_strdup_printf("/memory@%lx", (long)addr);
qemu_fdt_add_subnode(fdt, mem_name);
qemu_fdt_setprop_cells(fdt, mem_name, "reg",
addr >> 32, addr, size >> 32, size);
qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
- riscv_socket_fdt_write_id(mc, mem_name, socket);
+ riscv_socket_fdt_write_id(ms, mem_name, socket);
g_free(mem_name);
clint_addr = memmap[SPIKE_CLINT].base +
@@ -167,14 +167,14 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
- riscv_socket_fdt_write_id(mc, clint_name, socket);
+ riscv_socket_fdt_write_id(ms, clint_name, socket);
g_free(clint_name);
g_free(clint_cells);
g_free(clust_name);
}
- riscv_socket_fdt_write_distance_matrix(mc);
+ riscv_socket_fdt_write_distance_matrix(ms);
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
@@ -324,9 +324,10 @@ static void spike_board_init(MachineState *machine)
kernel_entry = 0;
}
- /* Compute the fdt load address in dram */
- fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
- machine->ram_size, machine->fdt);
+ fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
+ memmap[SPIKE_DRAM].size,
+ machine);
+ riscv_load_fdt(fdt_load_addr, machine->fdt);
/* load the reset vector */
riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4a11b4b..b81081c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -227,7 +227,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
{
int cpu;
uint32_t cpu_phandle;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
char *name, *cpu_name, *core_name, *intc_name;
bool is_32_bit = riscv_is_32bit(&s->soc[0]);
@@ -236,40 +236,40 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
cpu_name = g_strdup_printf("/cpus/cpu@%d",
s->soc[socket].hartid_base + cpu);
- qemu_fdt_add_subnode(mc->fdt, cpu_name);
+ qemu_fdt_add_subnode(ms->fdt, cpu_name);
if (riscv_feature(&s->soc[socket].harts[cpu].env,
RISCV_FEATURE_MMU)) {
- qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
+ qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
(is_32_bit) ? "riscv,sv32" : "riscv,sv48");
} else {
- qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
+ qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
"riscv,none");
}
name = riscv_isa_string(&s->soc[socket].harts[cpu]);
- qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
+ qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
g_free(name);
- qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv");
- qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay");
- qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg",
+ qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
+ qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay");
+ qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg",
s->soc[socket].hartid_base + cpu);
- qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu");
- riscv_socket_fdt_write_id(mc, cpu_name, socket);
- qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle);
+ qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu");
+ riscv_socket_fdt_write_id(ms, cpu_name, socket);
+ qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle);
intc_phandles[cpu] = (*phandle)++;
intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
- qemu_fdt_add_subnode(mc->fdt, intc_name);
- qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
+ qemu_fdt_add_subnode(ms->fdt, intc_name);
+ qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle",
intc_phandles[cpu]);
- qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
+ qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible",
"riscv,cpu-intc");
- qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
+ qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1);
core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
- qemu_fdt_add_subnode(mc->fdt, core_name);
- qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle);
+ qemu_fdt_add_subnode(ms->fdt, core_name);
+ qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle);
g_free(core_name);
g_free(intc_name);
@@ -282,16 +282,16 @@ static void create_fdt_socket_memory(RISCVVirtState *s,
{
char *mem_name;
uint64_t addr, size;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
- addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
- size = riscv_socket_mem_size(mc, socket);
+ addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket);
+ size = riscv_socket_mem_size(ms, socket);
mem_name = g_strdup_printf("/memory@%lx", (long)addr);
- qemu_fdt_add_subnode(mc->fdt, mem_name);
- qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg",
+ qemu_fdt_add_subnode(ms->fdt, mem_name);
+ qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg",
addr >> 32, addr, size >> 32, size);
- qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory");
- riscv_socket_fdt_write_id(mc, mem_name, socket);
+ qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory");
+ riscv_socket_fdt_write_id(ms, mem_name, socket);
g_free(mem_name);
}
@@ -303,7 +303,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
char *clint_name;
uint32_t *clint_cells;
unsigned long clint_addr;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
static const char * const clint_compat[2] = {
"sifive,clint0", "riscv,clint0"
};
@@ -319,15 +319,15 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
- qemu_fdt_add_subnode(mc->fdt, clint_name);
- qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible",
+ qemu_fdt_add_subnode(ms->fdt, clint_name);
+ qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible",
(char **)&clint_compat,
ARRAY_SIZE(clint_compat));
- qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg",
0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
- qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended",
+ qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended",
clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
- riscv_socket_fdt_write_id(mc, clint_name, socket);
+ riscv_socket_fdt_write_id(ms, clint_name, socket);
g_free(clint_name);
g_free(clint_cells);
@@ -344,7 +344,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
uint32_t *aclint_mswi_cells;
uint32_t *aclint_sswi_cells;
uint32_t *aclint_mtimer_cells;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
@@ -363,16 +363,16 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
name = g_strdup_printf("/soc/mswi@%lx", addr);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible",
"riscv,aclint-mswi");
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
- qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+ qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
aclint_mswi_cells, aclint_cells_size);
- qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
- riscv_socket_fdt_write_id(mc, name, socket);
+ qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
+ riscv_socket_fdt_write_id(ms, name, socket);
g_free(name);
}
@@ -386,33 +386,33 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE;
}
name = g_strdup_printf("/soc/mtimer@%lx", addr);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible",
"riscv,aclint-mtimer");
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
0x0, size - RISCV_ACLINT_DEFAULT_MTIME,
0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
0x0, RISCV_ACLINT_DEFAULT_MTIME);
- qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+ qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
aclint_mtimer_cells, aclint_cells_size);
- riscv_socket_fdt_write_id(mc, name, socket);
+ riscv_socket_fdt_write_id(ms, name, socket);
g_free(name);
if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
addr = memmap[VIRT_ACLINT_SSWI].base +
(memmap[VIRT_ACLINT_SSWI].size * socket);
name = g_strdup_printf("/soc/sswi@%lx", addr);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible",
"riscv,aclint-sswi");
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
- qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+ qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
aclint_sswi_cells, aclint_cells_size);
- qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
- riscv_socket_fdt_write_id(mc, name, socket);
+ qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
+ riscv_socket_fdt_write_id(ms, name, socket);
g_free(name);
}
@@ -430,7 +430,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
char *plic_name;
uint32_t *plic_cells;
unsigned long plic_addr;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
static const char * const plic_compat[2] = {
"sifive,plic-1.0.0", "riscv,plic0"
};
@@ -456,27 +456,27 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
plic_phandles[socket] = (*phandle)++;
plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
- qemu_fdt_add_subnode(mc->fdt, plic_name);
- qemu_fdt_setprop_cell(mc->fdt, plic_name,
+ qemu_fdt_add_subnode(ms->fdt, plic_name);
+ qemu_fdt_setprop_cell(ms->fdt, plic_name,
"#interrupt-cells", FDT_PLIC_INT_CELLS);
- qemu_fdt_setprop_cell(mc->fdt, plic_name,
+ qemu_fdt_setprop_cell(ms->fdt, plic_name,
"#address-cells", FDT_PLIC_ADDR_CELLS);
- qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
+ qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible",
(char **)&plic_compat,
ARRAY_SIZE(plic_compat));
- qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended",
+ qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended",
plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
- qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg",
0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
- qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev",
+ qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev",
VIRT_IRQCHIP_NUM_SOURCES - 1);
- riscv_socket_fdt_write_id(mc, plic_name, socket);
- qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
+ riscv_socket_fdt_write_id(ms, plic_name, socket);
+ qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle",
plic_phandles[socket]);
if (!socket) {
- platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
+ platform_bus_add_all_fdt_nodes(ms->fdt, plic_name,
memmap[VIRT_PLATFORM_BUS].base,
memmap[VIRT_PLATFORM_BUS].size,
VIRT_PLATFORM_BUS_IRQ);
@@ -504,22 +504,23 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
{
int cpu, socket;
char *imsic_name;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
+ int socket_count = riscv_socket_count(ms);
uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
*msi_m_phandle = (*phandle)++;
*msi_s_phandle = (*phandle)++;
- imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2);
- imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4);
+ imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2);
+ imsic_regs = g_new0(uint32_t, socket_count * 4);
/* M-level IMSIC node */
- for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
+ for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
}
imsic_max_hart_per_socket = 0;
- for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+ for (socket = 0; socket < socket_count; socket++) {
imsic_addr = memmap[VIRT_IMSIC_M].base +
socket * VIRT_IMSIC_GROUP_MAX_SIZE;
imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts;
@@ -533,41 +534,41 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
}
imsic_name = g_strdup_printf("/soc/imsics@%lx",
(unsigned long)memmap[VIRT_IMSIC_M].base);
- qemu_fdt_add_subnode(mc->fdt, imsic_name);
- qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
+ qemu_fdt_add_subnode(ms->fdt, imsic_name);
+ qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
"riscv,imsics");
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
FDT_IMSIC_INT_CELLS);
- qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
+ qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
NULL, 0);
- qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
+ qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
NULL, 0);
- qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
- imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
- qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
- riscv_socket_count(mc) * sizeof(uint32_t) * 4);
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
+ qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
+ imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
+ qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
+ socket_count * sizeof(uint32_t) * 4);
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
VIRT_IRQCHIP_NUM_MSIS);
- if (riscv_socket_count(mc) > 1) {
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
+ if (socket_count > 1) {
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
imsic_num_bits(imsic_max_hart_per_socket));
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
- imsic_num_bits(riscv_socket_count(mc)));
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
+ imsic_num_bits(socket_count));
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
IMSIC_MMIO_GROUP_MIN_SHIFT);
}
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle);
g_free(imsic_name);
/* S-level IMSIC node */
- for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
+ for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
}
imsic_guest_bits = imsic_num_bits(s->aia_guests + 1);
imsic_max_hart_per_socket = 0;
- for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+ for (socket = 0; socket < socket_count; socket++) {
imsic_addr = memmap[VIRT_IMSIC_S].base +
socket * VIRT_IMSIC_GROUP_MAX_SIZE;
imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
@@ -582,34 +583,34 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
}
imsic_name = g_strdup_printf("/soc/imsics@%lx",
(unsigned long)memmap[VIRT_IMSIC_S].base);
- qemu_fdt_add_subnode(mc->fdt, imsic_name);
- qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
+ qemu_fdt_add_subnode(ms->fdt, imsic_name);
+ qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
"riscv,imsics");
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
FDT_IMSIC_INT_CELLS);
- qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
+ qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
NULL, 0);
- qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
+ qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
NULL, 0);
- qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
- imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
- qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
- riscv_socket_count(mc) * sizeof(uint32_t) * 4);
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
+ qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
+ imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
+ qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
+ socket_count * sizeof(uint32_t) * 4);
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
VIRT_IRQCHIP_NUM_MSIS);
if (imsic_guest_bits) {
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits",
imsic_guest_bits);
}
- if (riscv_socket_count(mc) > 1) {
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
+ if (socket_count > 1) {
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
imsic_num_bits(imsic_max_hart_per_socket));
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
- imsic_num_bits(riscv_socket_count(mc)));
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
+ imsic_num_bits(socket_count));
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
IMSIC_MMIO_GROUP_MIN_SHIFT);
}
- qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle);
+ qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle);
g_free(imsic_name);
g_free(imsic_regs);
@@ -628,7 +629,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
char *aplic_name;
uint32_t *aplic_cells;
unsigned long aplic_addr;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
uint32_t aplic_m_phandle, aplic_s_phandle;
aplic_m_phandle = (*phandle)++;
@@ -643,28 +644,28 @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
aplic_addr = memmap[VIRT_APLIC_M].base +
(memmap[VIRT_APLIC_M].size * socket);
aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
- qemu_fdt_add_subnode(mc->fdt, aplic_name);
- qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
- qemu_fdt_setprop_cell(mc->fdt, aplic_name,
+ qemu_fdt_add_subnode(ms->fdt, aplic_name);
+ qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name,
"#interrupt-cells", FDT_APLIC_INT_CELLS);
- qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
- qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
+ qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
} else {
- qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
msi_m_phandle);
}
- qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
- qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
VIRT_IRQCHIP_NUM_SOURCES);
- qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children",
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children",
aplic_s_phandle);
- qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate",
+ qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate",
aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
- riscv_socket_fdt_write_id(mc, aplic_name, socket);
- qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle);
+ riscv_socket_fdt_write_id(ms, aplic_name, socket);
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle);
g_free(aplic_name);
/* S-level APLIC node */
@@ -675,27 +676,27 @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
aplic_addr = memmap[VIRT_APLIC_S].base +
(memmap[VIRT_APLIC_S].size * socket);
aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
- qemu_fdt_add_subnode(mc->fdt, aplic_name);
- qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
- qemu_fdt_setprop_cell(mc->fdt, aplic_name,
+ qemu_fdt_add_subnode(ms->fdt, aplic_name);
+ qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name,
"#interrupt-cells", FDT_APLIC_INT_CELLS);
- qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
- qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
+ qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
} else {
- qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
msi_s_phandle);
}
- qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
- qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
VIRT_IRQCHIP_NUM_SOURCES);
- riscv_socket_fdt_write_id(mc, aplic_name, socket);
- qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
+ riscv_socket_fdt_write_id(ms, aplic_name, socket);
+ qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle);
if (!socket) {
- platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
+ platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name,
memmap[VIRT_PLATFORM_BUS].base,
memmap[VIRT_PLATFORM_BUS].size,
VIRT_PLATFORM_BUS_IRQ);
@@ -710,13 +711,13 @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
static void create_fdt_pmu(RISCVVirtState *s)
{
char *pmu_name;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
RISCVCPU hart = s->soc[0].harts[0];
pmu_name = g_strdup_printf("/soc/pmu");
- qemu_fdt_add_subnode(mc->fdt, pmu_name);
- qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu");
- riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name);
+ qemu_fdt_add_subnode(ms->fdt, pmu_name);
+ qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu");
+ riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name);
g_free(pmu_name);
}
@@ -730,25 +731,26 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
{
char *clust_name;
int socket, phandle_pos;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
uint32_t *intc_phandles, xplic_phandles[MAX_NODES];
+ int socket_count = riscv_socket_count(ms);
- qemu_fdt_add_subnode(mc->fdt, "/cpus");
- qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
+ qemu_fdt_add_subnode(ms->fdt, "/cpus");
+ qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency",
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
- qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0);
- qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1);
- qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map");
+ qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
+ qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
+ qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
- intc_phandles = g_new0(uint32_t, mc->smp.cpus);
+ intc_phandles = g_new0(uint32_t, ms->smp.cpus);
- phandle_pos = mc->smp.cpus;
- for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+ phandle_pos = ms->smp.cpus;
+ for (socket = (socket_count - 1); socket >= 0; socket--) {
phandle_pos -= s->soc[socket].num_harts;
clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
- qemu_fdt_add_subnode(mc->fdt, clust_name);
+ qemu_fdt_add_subnode(ms->fdt, clust_name);
create_fdt_socket_cpus(s, socket, clust_name, phandle,
&intc_phandles[phandle_pos]);
@@ -774,8 +776,8 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
*msi_pcie_phandle = msi_s_phandle;
}
- phandle_pos = mc->smp.cpus;
- for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+ phandle_pos = ms->smp.cpus;
+ for (socket = (socket_count - 1); socket >= 0; socket--) {
phandle_pos -= s->soc[socket].num_harts;
if (s->aia_type == VIRT_AIA_TYPE_NONE) {
@@ -790,7 +792,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
g_free(intc_phandles);
- for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+ for (socket = 0; socket < socket_count; socket++) {
if (socket == 0) {
*irq_mmio_phandle = xplic_phandles[socket];
*irq_virtio_phandle = xplic_phandles[socket];
@@ -805,7 +807,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
}
}
- riscv_socket_fdt_write_distance_matrix(mc);
+ riscv_socket_fdt_write_distance_matrix(ms);
}
static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
@@ -813,23 +815,23 @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
{
int i;
char *name;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
for (i = 0; i < VIRTIO_COUNT; i++) {
name = g_strdup_printf("/soc/virtio_mmio@%lx",
(long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio");
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio");
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
0x0, memmap[VIRT_VIRTIO].size);
- qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
+ qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
irq_virtio_phandle);
if (s->aia_type == VIRT_AIA_TYPE_NONE) {
- qemu_fdt_setprop_cell(mc->fdt, name, "interrupts",
+ qemu_fdt_setprop_cell(ms->fdt, name, "interrupts",
VIRTIO_IRQ + i);
} else {
- qemu_fdt_setprop_cells(mc->fdt, name, "interrupts",
+ qemu_fdt_setprop_cells(ms->fdt, name, "interrupts",
VIRTIO_IRQ + i, 0x4);
}
g_free(name);
@@ -841,29 +843,29 @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
uint32_t msi_pcie_phandle)
{
char *name;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
name = g_strdup_printf("/soc/pci@%lx",
(long) memmap[VIRT_PCIE_ECAM].base);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells",
FDT_PCI_ADDR_CELLS);
- qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells",
+ qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells",
FDT_PCI_INT_CELLS);
- qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+ qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible",
"pci-host-ecam-generic");
- qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci");
- qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0);
- qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0,
+ qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci");
+ qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0);
+ qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0,
memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
- qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0);
+ qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0);
if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
- qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle);
+ qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle);
}
- qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0,
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0,
memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
- qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges",
+ qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges",
1, FDT_PCI_RANGE_IOPORT, 2, 0,
2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
1, FDT_PCI_RANGE_MMIO,
@@ -873,7 +875,7 @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
2, virt_high_pcie_memmap.base,
2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
- create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle);
+ create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle);
g_free(name);
}
@@ -882,39 +884,39 @@ static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap,
{
char *name;
uint32_t test_phandle;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
test_phandle = (*phandle)++;
name = g_strdup_printf("/soc/test@%lx",
(long)memmap[VIRT_TEST].base);
- qemu_fdt_add_subnode(mc->fdt, name);
+ qemu_fdt_add_subnode(ms->fdt, name);
{
static const char * const compat[3] = {
"sifive,test1", "sifive,test0", "syscon"
};
- qemu_fdt_setprop_string_array(mc->fdt, name, "compatible",
+ qemu_fdt_setprop_string_array(ms->fdt, name, "compatible",
(char **)&compat, ARRAY_SIZE(compat));
}
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size);
- qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle);
- test_phandle = qemu_fdt_get_phandle(mc->fdt, name);
+ qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle);
+ test_phandle = qemu_fdt_get_phandle(ms->fdt, name);
g_free(name);
name = g_strdup_printf("/reboot");
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot");
- qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
- qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
- qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET);
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot");
+ qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
+ qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
+ qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET);
g_free(name);
name = g_strdup_printf("/poweroff");
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff");
- qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
- qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
- qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS);
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff");
+ qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
+ qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
+ qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS);
g_free(name);
}
@@ -922,24 +924,24 @@ static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap,
uint32_t irq_mmio_phandle)
{
char *name;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a");
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a");
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, memmap[VIRT_UART0].base,
0x0, memmap[VIRT_UART0].size);
- qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400);
- qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle);
+ qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400);
+ qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle);
if (s->aia_type == VIRT_AIA_TYPE_NONE) {
- qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
+ qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ);
} else {
- qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4);
+ qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4);
}
- qemu_fdt_add_subnode(mc->fdt, "/chosen");
- qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name);
+ qemu_fdt_add_subnode(ms->fdt, "/chosen");
+ qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name);
g_free(name);
}
@@ -947,20 +949,20 @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
uint32_t irq_mmio_phandle)
{
char *name;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible",
"google,goldfish-rtc");
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size);
- qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
+ qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
irq_mmio_phandle);
if (s->aia_type == VIRT_AIA_TYPE_NONE) {
- qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
+ qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ);
} else {
- qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4);
+ qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4);
}
g_free(name);
}
@@ -968,68 +970,68 @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap)
{
char *name;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
name = g_strdup_printf("/flash@%" PRIx64, flashbase);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
- qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
+ qemu_fdt_add_subnode(ms->fdt, name);
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash");
+ qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
2, flashbase, 2, flashsize,
2, flashbase + flashsize, 2, flashsize);
- qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
+ qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4);
g_free(name);
}
static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
{
char *nodename;
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
hwaddr base = memmap[VIRT_FW_CFG].base;
hwaddr size = memmap[VIRT_FW_CFG].size;
nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
- qemu_fdt_add_subnode(mc->fdt, nodename);
- qemu_fdt_setprop_string(mc->fdt, nodename,
+ qemu_fdt_add_subnode(ms->fdt, nodename);
+ qemu_fdt_setprop_string(ms->fdt, nodename,
"compatible", "qemu,fw-cfg-mmio");
- qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
2, base, 2, size);
- qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+ qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
g_free(nodename);
}
static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
{
- MachineState *mc = MACHINE(s);
+ MachineState *ms = MACHINE(s);
uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
uint8_t rng_seed[32];
- if (mc->dtb) {
- mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
- if (!mc->fdt) {
+ if (ms->dtb) {
+ ms->fdt = load_device_tree(ms->dtb, &s->fdt_size);
+ if (!ms->fdt) {
error_report("load_device_tree() failed");
exit(1);
}
} else {
- mc->fdt = create_device_tree(&s->fdt_size);
- if (!mc->fdt) {
+ ms->fdt = create_device_tree(&s->fdt_size);
+ if (!ms->fdt) {
error_report("create_device_tree() failed");
exit(1);
}
}
- qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu");
- qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio");
- qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2);
- qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2);
+ qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu");
+ qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio");
+ qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2);
+ qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2);
- qemu_fdt_add_subnode(mc->fdt, "/soc");
- qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0);
- qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus");
- qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2);
- qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
+ qemu_fdt_add_subnode(ms->fdt, "/soc");
+ qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0);
+ qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus");
+ qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2);
+ qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2);
create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle,
&irq_pcie_phandle, &irq_virtio_phandle,
@@ -1051,7 +1053,8 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
/* Pass seed to RNG */
qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
- qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
+ qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed",
+ rng_seed, sizeof(rng_seed));
}
static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
@@ -1103,14 +1106,14 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
return dev;
}
-static FWCfgState *create_fw_cfg(const MachineState *mc)
+static FWCfgState *create_fw_cfg(const MachineState *ms)
{
hwaddr base = virt_memmap[VIRT_FW_CFG].base;
FWCfgState *fw_cfg;
fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
&address_space_memory);
- fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
return fw_cfg;
}
@@ -1300,9 +1303,11 @@ static void virt_machine_done(Notifier *notifier, void *data)
start_addr = virt_memmap[VIRT_FLASH].base;
}
- /* Compute the fdt load address in dram */
- fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
- machine->ram_size, machine->fdt);
+ fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
+ memmap[VIRT_DRAM].size,
+ machine);
+ riscv_load_fdt(fdt_load_addr, machine->fdt);
+
/* load the reset vector */
riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
virt_memmap[VIRT_MROM].base,
@@ -1328,9 +1333,10 @@ static void virt_machine_init(MachineState *machine)
char *soc_name;
DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
int i, base_hartid, hart_count;
+ int socket_count = riscv_socket_count(machine);
/* Check socket count limit */
- if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
+ if (VIRT_SOCKETS_MAX < socket_count) {
error_report("number of sockets/nodes should be less than %d",
VIRT_SOCKETS_MAX);
exit(1);
@@ -1338,7 +1344,7 @@ static void virt_machine_init(MachineState *machine)
/* Initialize sockets */
mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL;
- for (i = 0; i < riscv_socket_count(machine); i++) {
+ for (i = 0; i < socket_count; i++) {
if (!riscv_socket_check_hartids(machine, i)) {
error_report("discontinuous hartids in socket%d", i);
exit(1);
@@ -1577,16 +1583,14 @@ static void virt_set_aia(Object *obj, const char *val, Error **errp)
static bool virt_get_aclint(Object *obj, Error **errp)
{
- MachineState *ms = MACHINE(obj);
- RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
return s->have_aclint;
}
static void virt_set_aclint(Object *obj, bool value, Error **errp)
{
- MachineState *ms = MACHINE(obj);
- RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
s->have_aclint = value;
}
generated by cgit v1.1 at 2024-09-28 16:14:13 +0000