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-rw-r--r--hw/ppc/Kconfig2
-rw-r--r--hw/ppc/e500.c59
-rw-r--r--hw/ppc/e500.h1
-rw-r--r--hw/ppc/e500plat.c1
-rw-r--r--hw/ppc/spapr.c1
-rw-r--r--hw/ppc/virtex_ml507.c2
-rw-r--r--hw/sd/sdhci-internal.h1
-rw-r--r--hw/sd/sdhci.c32
8 files changed, 87 insertions, 12 deletions
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index b8d2522..72a311e 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -128,10 +128,12 @@ config E500
select PFLASH_CFI01
select PLATFORM_BUS
select PPCE500_PCI
+ select SDHCI
select SERIAL
select MPC_I2C
select FDT_PPC
select DS1338
+ select UNIMP
config E500PLAT
bool
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 2fe4966..9fa1f8e 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -48,6 +48,8 @@
#include "hw/net/fsl_etsec/etsec.h"
#include "hw/i2c/i2c.h"
#include "hw/irq.h"
+#include "hw/sd/sdhci.h"
+#include "hw/misc/unimp.h"
#define EPAPR_MAGIC (0x45504150)
#define DTC_LOAD_PAD 0x1800000
@@ -66,11 +68,14 @@
#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
#define MPC8544_PCI_REGS_OFFSET 0x8000ULL
#define MPC8544_PCI_REGS_SIZE 0x1000ULL
+#define MPC85XX_ESDHC_REGS_OFFSET 0x2e000ULL
+#define MPC85XX_ESDHC_REGS_SIZE 0x1000ULL
#define MPC8544_UTIL_OFFSET 0xe0000ULL
#define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
#define MPC8544_I2C_REGS_OFFSET 0x3000ULL
#define MPC8XXX_GPIO_IRQ 47
#define MPC8544_I2C_IRQ 43
+#define MPC85XX_ESDHC_IRQ 72
#define RTC_REGS_OFFSET 0x68
#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
@@ -203,6 +208,22 @@ static void dt_i2c_create(void *fdt, const char *soc, const char *mpic,
g_free(i2c);
}
+static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic)
+{
+ hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET;
+ hwaddr size = MPC85XX_ESDHC_REGS_SIZE;
+ int irq = MPC85XX_ESDHC_IRQ;
+ g_autofree char *name = NULL;
+
+ name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio);
+ qemu_fdt_add_subnode(fdt, name);
+ qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0);
+ qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic);
+ qemu_fdt_setprop_cells(fdt, name, "bus-width", 4);
+ qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2);
+ qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size);
+ qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc");
+}
typedef struct PlatformDevtreeData {
void *fdt;
@@ -553,6 +574,10 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
dt_rtc_create(fdt, "i2c", "rtc");
+ /* sdhc */
+ if (pmc->has_esdhc) {
+ dt_sdhc_create(fdt, soc, mpic);
+ }
gutil = g_strdup_printf("%s/global-utilities@%llx", soc,
MPC8544_UTIL_OFFSET);
@@ -692,7 +717,6 @@ static int ppce500_prep_device_tree(PPCE500MachineState *machine,
kernel_base, kernel_size, true);
}
-/* Create -kernel TLB entries for BookE. */
hwaddr booke206_page_size_to_tlb(uint64_t size)
{
return 63 - clz64(size / KiB);
@@ -723,6 +747,7 @@ static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
return (1ULL << 10 << tsize);
}
+/* Create -kernel TLB entries for BookE. */
static void mmubooke_create_initial_mapping(CPUPPCState *env)
{
ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
@@ -883,7 +908,7 @@ void ppce500_init(MachineState *machine)
bool kernel_as_payload;
hwaddr bios_entry = 0;
target_long payload_size;
- struct boot_info *boot_info;
+ struct boot_info *boot_info = NULL;
int dt_size;
int i;
unsigned int smp_cpus = machine->smp.cpus;
@@ -938,7 +963,6 @@ void ppce500_init(MachineState *machine)
/* Register reset handler */
if (!i) {
/* Primary CPU */
- struct boot_info *boot_info;
boot_info = g_new0(struct boot_info, 1);
qemu_register_reset(ppce500_cpu_reset, cpu);
env->load_info = boot_info;
@@ -959,8 +983,7 @@ void ppce500_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, 0, machine->ram);
dev = qdev_new("e500-ccsr");
- object_property_add_child(qdev_get_machine(), "e500-ccsr",
- OBJECT(dev));
+ object_property_add_child(OBJECT(machine), "e500-ccsr", OBJECT(dev));
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ccsr = CCSR(dev);
ccsr_addr_space = &ccsr->ccsr_space;
@@ -982,7 +1005,8 @@ void ppce500_init(MachineState *machine)
0, qdev_get_gpio_in(mpicdev, 42), 399193,
serial_hd(1), DEVICE_BIG_ENDIAN);
}
- /* I2C */
+
+ /* I2C */
dev = qdev_new("mpc-i2c");
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
@@ -992,6 +1016,26 @@ void ppce500_init(MachineState *machine)
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
+ /* eSDHC */
+ if (pmc->has_esdhc) {
+ create_unimplemented_device("esdhc",
+ pmc->ccsrbar_base + MPC85XX_ESDHC_REGS_OFFSET,
+ MPC85XX_ESDHC_REGS_SIZE);
+
+ /*
+ * Compatible with:
+ * - SD Host Controller Specification Version 2.0 Part A2
+ * (See MPC8569E Reference Manual)
+ */
+ dev = qdev_new(TYPE_SYSBUS_SDHCI);
+ qdev_prop_set_uint8(dev, "sd-spec-version", 2);
+ qdev_prop_set_uint8(dev, "endianness", DEVICE_BIG_ENDIAN);
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ));
+ memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET,
+ sysbus_mmio_get_region(s, 0));
+ }
/* General Utility device */
dev = qdev_new("mpc8544-guts");
@@ -1002,7 +1046,7 @@ void ppce500_init(MachineState *machine)
/* PCI */
dev = qdev_new("e500-pcihost");
- object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev));
+ object_property_add_child(OBJECT(machine), "pci-host", OBJECT(dev));
qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);
qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
s = SYS_BUS_DEVICE(dev);
@@ -1217,7 +1261,6 @@ void ppce500_init(MachineState *machine)
}
assert(dt_size < DTB_MAX_SIZE);
- boot_info = env->load_info;
boot_info->entry = bios_entry;
boot_info->dt_base = dt_base;
boot_info->dt_size = dt_size;
diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
index 68f754c..8c09ef9 100644
--- a/hw/ppc/e500.h
+++ b/hw/ppc/e500.h
@@ -27,6 +27,7 @@ struct PPCE500MachineClass {
int mpic_version;
bool has_mpc8xxx_gpio;
+ bool has_esdhc;
hwaddr platform_bus_base;
hwaddr platform_bus_size;
int platform_bus_first_irq;
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index 5bb1c60..44bf874 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -86,6 +86,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data)
pmc->fixup_devtree = e500plat_fixup_devtree;
pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_42;
pmc->has_mpc8xxx_gpio = true;
+ pmc->has_esdhc = true;
pmc->platform_bus_base = 0xf00000000ULL;
pmc->platform_bus_size = 128 * MiB;
pmc->platform_bus_first_irq = 5;
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index f067879..4921198 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -62,6 +62,7 @@
#include "hw/ppc/fdt.h"
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_vio.h"
+#include "hw/ppc/vof.h"
#include "hw/qdev-properties.h"
#include "hw/pci-host/spapr.h"
#include "hw/pci/msi.h"
diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
index 13cace2..f2f81bd 100644
--- a/hw/ppc/virtex_ml507.c
+++ b/hw/ppc/virtex_ml507.c
@@ -157,7 +157,7 @@ static int xilinx_load_device_tree(MachineState *machine,
int r;
const char *dtb_filename;
- dtb_filename = current_machine->dtb;
+ dtb_filename = machine->dtb;
if (dtb_filename) {
fdt = load_device_tree(dtb_filename, &fdt_size);
if (!fdt) {
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index 964570f..5f3765f 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -308,6 +308,7 @@ extern const VMStateDescription sdhci_vmstate;
#define SDHC_CAPAB_REG_DEFAULT 0x057834b4
#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
+ DEFINE_PROP_UINT8("endianness", _state, endianness, DEVICE_LITTLE_ENDIAN), \
DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \
DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \
DEFINE_PROP_UINT8("vendor", _state, vendor, SDHCI_VENDOR_NONE), \
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 306070c..6811f0f 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1329,7 +1329,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
value >> shift, value >> shift);
}
-static const MemoryRegionOps sdhci_mmio_ops = {
+static const MemoryRegionOps sdhci_mmio_le_ops = {
.read = sdhci_read,
.write = sdhci_write,
.valid = {
@@ -1340,6 +1340,21 @@ static const MemoryRegionOps sdhci_mmio_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
+static const MemoryRegionOps sdhci_mmio_be_ops = {
+ .read = sdhci_read,
+ .write = sdhci_write,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ .unaligned = false
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
{
ERRP_GUARD();
@@ -1367,8 +1382,6 @@ void sdhci_initfn(SDHCIState *s)
s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
-
- s->io_ops = &sdhci_mmio_ops;
}
void sdhci_uninitfn(SDHCIState *s)
@@ -1384,10 +1397,23 @@ void sdhci_common_realize(SDHCIState *s, Error **errp)
{
ERRP_GUARD();
+ switch (s->endianness) {
+ case DEVICE_LITTLE_ENDIAN:
+ s->io_ops = &sdhci_mmio_le_ops;
+ break;
+ case DEVICE_BIG_ENDIAN:
+ s->io_ops = &sdhci_mmio_be_ops;
+ break;
+ default:
+ error_setg(errp, "Incorrect endianness");
+ return;
+ }
+
sdhci_init_readonly_registers(s, errp);
if (*errp) {
return;
}
+
s->buf_maxsz = sdhci_get_fifolen(s);
s->fifo_buffer = g_malloc0(s->buf_maxsz);
generated by cgit v1.1 at 2024-08-18 19:30:32 +0000