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Diffstat (limited to 'hw/pci-bridge/cxl_root_port.c')
| -rw-r--r-- | hw/pci-bridge/cxl_root_port.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 5824ba3..c0037f2 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -211,7 +211,6 @@ static const Property gen_rp_props[] = { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_32), - DEFINE_PROP_END_OF_LIST() }; static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr, |