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-rw-r--r--hw/dma/i82374.c9
-rw-r--r--hw/dma/pl330.c4
-rw-r--r--hw/dma/puv3_dma.c9
-rw-r--r--hw/dma/pxa2xx_dma.c9
-rw-r--r--hw/dma/rc4030.c10
-rw-r--r--hw/dma/sparc32_dma.c2
-rw-r--r--hw/dma/xilinx_axidma.c23
7 files changed, 39 insertions, 27 deletions
diff --git a/hw/dma/i82374.c b/hw/dma/i82374.c
index 6977d85..5b7ff63 100644
--- a/hw/dma/i82374.c
+++ b/hw/dma/i82374.c
@@ -29,9 +29,12 @@
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "hw/dma/i8257.h"
+#include "qom/object.h"
#define TYPE_I82374 "i82374"
-#define I82374(obj) OBJECT_CHECK(I82374State, (obj), TYPE_I82374)
+typedef struct I82374State I82374State;
+DECLARE_INSTANCE_CHECKER(I82374State, I82374,
+ TYPE_I82374)
//#define DEBUG_I82374
@@ -45,13 +48,13 @@ do {} while (0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "i82374 ERROR: " fmt , ## __VA_ARGS__); } while (0)
-typedef struct I82374State {
+struct I82374State {
ISADevice parent_obj;
uint32_t iobase;
uint8_t commands[8];
PortioList port_list;
-} I82374State;
+};
static const VMStateDescription vmstate_i82374 = {
.name = "i82374",
diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c
index 0bd63a4..859586f 100644
--- a/hw/dma/pl330.c
+++ b/hw/dma/pl330.c
@@ -26,6 +26,7 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "trace.h"
+#include "qom/object.h"
#ifndef PL330_ERR_DEBUG
#define PL330_ERR_DEBUG 0
@@ -271,7 +272,8 @@ struct PL330State {
};
#define TYPE_PL330 "pl330"
-#define PL330(obj) OBJECT_CHECK(PL330State, (obj), TYPE_PL330)
+DECLARE_INSTANCE_CHECKER(PL330State, PL330,
+ TYPE_PL330)
static const VMStateDescription vmstate_pl330 = {
.name = "pl330",
diff --git a/hw/dma/puv3_dma.c b/hw/dma/puv3_dma.c
index 7fa9791..825e3dc 100644
--- a/hw/dma/puv3_dma.c
+++ b/hw/dma/puv3_dma.c
@@ -11,6 +11,7 @@
#include "qemu/osdep.h"
#include "hw/sysbus.h"
+#include "qom/object.h"
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
@@ -22,14 +23,16 @@
#define PUV3_DMA_CH(offset) ((offset) >> 8)
#define TYPE_PUV3_DMA "puv3_dma"
-#define PUV3_DMA(obj) OBJECT_CHECK(PUV3DMAState, (obj), TYPE_PUV3_DMA)
+typedef struct PUV3DMAState PUV3DMAState;
+DECLARE_INSTANCE_CHECKER(PUV3DMAState, PUV3_DMA,
+ TYPE_PUV3_DMA)
-typedef struct PUV3DMAState {
+struct PUV3DMAState {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t reg_CFG[PUV3_DMA_CH_NR];
-} PUV3DMAState;
+};
static uint64_t puv3_dma_read(void *opaque, hwaddr offset,
unsigned size)
diff --git a/hw/dma/pxa2xx_dma.c b/hw/dma/pxa2xx_dma.c
index 78b2849..4f6c0e5 100644
--- a/hw/dma/pxa2xx_dma.c
+++ b/hw/dma/pxa2xx_dma.c
@@ -18,6 +18,7 @@
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/module.h"
+#include "qom/object.h"
#define PXA255_DMA_NUM_CHANNELS 16
#define PXA27X_DMA_NUM_CHANNELS 32
@@ -34,9 +35,11 @@ typedef struct {
} PXA2xxDMAChannel;
#define TYPE_PXA2XX_DMA "pxa2xx-dma"
-#define PXA2XX_DMA(obj) OBJECT_CHECK(PXA2xxDMAState, (obj), TYPE_PXA2XX_DMA)
+typedef struct PXA2xxDMAState PXA2xxDMAState;
+DECLARE_INSTANCE_CHECKER(PXA2xxDMAState, PXA2XX_DMA,
+ TYPE_PXA2XX_DMA)
-typedef struct PXA2xxDMAState {
+struct PXA2xxDMAState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@@ -58,7 +61,7 @@ typedef struct PXA2xxDMAState {
/* Flag to avoid recursive DMA invocations. */
int running;
-} PXA2xxDMAState;
+};
#define DCSR0 0x0000 /* DMA Control / Status register for Channel 0 */
#define DCSR31 0x007c /* DMA Control / Status register for Channel 31 */
diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c
index 7eddc9a..c584815 100644
--- a/hw/dma/rc4030.c
+++ b/hw/dma/rc4030.c
@@ -34,6 +34,7 @@
#include "qemu/module.h"
#include "exec/address-spaces.h"
#include "trace.h"
+#include "qom/object.h"
/********************************************************/
/* rc4030 emulation */
@@ -55,12 +56,13 @@ typedef struct dma_pagetable_entry {
#define DMA_FLAG_ADDR_INTR 0x0400
#define TYPE_RC4030 "rc4030"
-#define RC4030(obj) \
- OBJECT_CHECK(rc4030State, (obj), TYPE_RC4030)
+typedef struct rc4030State rc4030State;
+DECLARE_INSTANCE_CHECKER(rc4030State, RC4030,
+ TYPE_RC4030)
#define TYPE_RC4030_IOMMU_MEMORY_REGION "rc4030-iommu-memory-region"
-typedef struct rc4030State {
+struct rc4030State {
SysBusDevice parent;
@@ -101,7 +103,7 @@ typedef struct rc4030State {
MemoryRegion iomem_chipset;
MemoryRegion iomem_jazzio;
-} rc4030State;
+};
static void set_next_tick(rc4030State *s)
{
diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c
index bcd1626..d20a5bc 100644
--- a/hw/dma/sparc32_dma.c
+++ b/hw/dma/sparc32_dma.c
@@ -303,7 +303,7 @@ static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)
d = qdev_new(TYPE_ESP);
object_property_add_child(OBJECT(dev), "esp", OBJECT(d));
- sysbus = ESP_STATE(d);
+ sysbus = ESP(d);
esp = &sysbus->esp;
esp->dma_memory_read = espdma_memory_read;
esp->dma_memory_write = espdma_memory_write;
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
index a4812e4..498fc17 100644
--- a/hw/dma/xilinx_axidma.c
+++ b/hw/dma/xilinx_axidma.c
@@ -35,6 +35,7 @@
#include "sysemu/dma.h"
#include "hw/stream.h"
+#include "qom/object.h"
#define D(x)
@@ -42,16 +43,16 @@
#define TYPE_XILINX_AXI_DMA_DATA_STREAM "xilinx-axi-dma-data-stream"
#define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream"
-#define XILINX_AXI_DMA(obj) \
- OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)
+typedef struct XilinxAXIDMA XilinxAXIDMA;
+DECLARE_INSTANCE_CHECKER(XilinxAXIDMA, XILINX_AXI_DMA,
+ TYPE_XILINX_AXI_DMA)
-#define XILINX_AXI_DMA_DATA_STREAM(obj) \
- OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
- TYPE_XILINX_AXI_DMA_DATA_STREAM)
+typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
+DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSlave, XILINX_AXI_DMA_DATA_STREAM,
+ TYPE_XILINX_AXI_DMA_DATA_STREAM)
-#define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
- OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
- TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
+DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSlave, XILINX_AXI_DMA_CONTROL_STREAM,
+ TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
#define R_DMACR (0x00 / 4)
#define R_DMASR (0x04 / 4)
@@ -62,8 +63,6 @@
#define CONTROL_PAYLOAD_WORDS 5
#define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
-typedef struct XilinxAXIDMA XilinxAXIDMA;
-typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
enum {
DMACR_RUNSTOP = 1,
@@ -634,7 +633,7 @@ static const TypeInfo axidma_info = {
static const TypeInfo xilinx_axidma_data_stream_info = {
.name = TYPE_XILINX_AXI_DMA_DATA_STREAM,
.parent = TYPE_OBJECT,
- .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
+ .instance_size = sizeof(XilinxAXIDMAStreamSlave),
.class_init = xilinx_axidma_stream_class_init,
.class_data = &xilinx_axidma_data_stream_class,
.interfaces = (InterfaceInfo[]) {
@@ -646,7 +645,7 @@ static const TypeInfo xilinx_axidma_data_stream_info = {
static const TypeInfo xilinx_axidma_control_stream_info = {
.name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
.parent = TYPE_OBJECT,
- .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
+ .instance_size = sizeof(XilinxAXIDMAStreamSlave),
.class_init = xilinx_axidma_stream_class_init,
.class_data = &xilinx_axidma_control_stream_class,
.interfaces = (InterfaceInfo[]) {
generated by cgit v1.1 at 2024-11-01 07:19:35 +0000