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-rw-r--r--hw/arm/aspeed.c18
-rw-r--r--hw/arm/boot.c6
-rw-r--r--hw/arm/collie.c16
-rw-r--r--hw/arm/cubieboard.c25
-rw-r--r--hw/arm/digic_boards.c40
-rw-r--r--hw/arm/highbank.c10
-rw-r--r--hw/arm/imx25_pdk.c19
-rw-r--r--hw/arm/integratorcp.c9
-rw-r--r--hw/arm/kzm.c18
-rw-r--r--hw/arm/mcimx6ul-evk.c25
-rw-r--r--hw/arm/mcimx7d-sabre.c25
-rw-r--r--hw/arm/mps2-tz.c15
-rw-r--r--hw/arm/mps2.c15
-rw-r--r--hw/arm/musicpal.c18
-rw-r--r--hw/arm/nseries.c32
-rw-r--r--hw/arm/omap_sx1.c20
-rw-r--r--hw/arm/palm.c19
-rw-r--r--hw/arm/raspi.c10
-rw-r--r--hw/arm/sabrelite.c23
-rw-r--r--hw/arm/sbsa-ref.c7
-rw-r--r--hw/arm/smmu-common.c3
-rw-r--r--hw/arm/smmuv3.c10
-rw-r--r--hw/arm/versatilepb.c7
-rw-r--r--hw/arm/vexpress.c14
-rw-r--r--hw/arm/virt.c7
-rw-r--r--hw/arm/xilinx_zynq.c20
-rw-r--r--hw/arm/xlnx-versal-virt.c7
-rw-r--r--hw/arm/xlnx-zcu102.c7
28 files changed, 222 insertions, 223 deletions
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index a17843f..a6a2102 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -35,7 +35,6 @@ static struct arm_boot_info aspeed_board_binfo = {
struct AspeedBoardState {
AspeedSoCState soc;
MemoryRegion ram_container;
- MemoryRegion ram;
MemoryRegion max_ram;
};
@@ -197,6 +196,7 @@ static void aspeed_machine_init(MachineState *machine)
memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
UINT32_MAX);
+ memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
object_initialize_child(OBJECT(machine), "soc", &bmc->soc,
(sizeof(bmc->soc)), amc->soc_name, &error_abort,
@@ -204,8 +204,12 @@ static void aspeed_machine_init(MachineState *machine)
sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
+ /*
+ * This will error out if isize is not supported by memory controller.
+ */
object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size",
- &error_abort);
+ &error_fatal);
+
object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap1, "hw-strap1",
&error_abort);
object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap2, "hw-strap2",
@@ -228,15 +232,6 @@ static void aspeed_machine_init(MachineState *machine)
object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
&error_abort);
- /*
- * Allocate RAM after the memory controller has checked the size
- * was valid. If not, a default value is used.
- */
- ram_size = object_property_get_uint(OBJECT(&bmc->soc), "ram-size",
- &error_abort);
-
- memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
- memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram);
memory_region_add_subregion(get_system_memory(),
sc->memmap[ASPEED_SDRAM],
&bmc->ram_container);
@@ -439,6 +434,7 @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data)
mc->no_floppy = 1;
mc->no_cdrom = 1;
mc->no_parallel = 1;
+ mc->default_ram_id = "ram";
aspeed_machine_class_props_init(oc);
}
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 0c213ca..fef4072 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -327,8 +327,7 @@ static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as)
cmdline_size = strlen(info->kernel_cmdline);
address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED,
- (const uint8_t *)info->kernel_cmdline,
- cmdline_size + 1);
+ info->kernel_cmdline, cmdline_size + 1);
cmdline_size = (cmdline_size >> 2) + 1;
WRITE_WORD(p, cmdline_size + 2);
WRITE_WORD(p, 0x54410009);
@@ -420,8 +419,7 @@ static void set_kernel_args_old(const struct arm_boot_info *info,
}
s = info->kernel_cmdline;
if (s) {
- address_space_write(as, p, MEMTXATTRS_UNSPECIFIED,
- (const uint8_t *)s, strlen(s) + 1);
+ address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1);
} else {
WRITE_WORD(p, 0);
}
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index 970a440..4992084 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -10,6 +10,7 @@
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
+#include "qemu/cutils.h"
#include "hw/sysbus.h"
#include "hw/boards.h"
#include "strongarm.h"
@@ -27,13 +28,18 @@ static void collie_init(MachineState *machine)
{
StrongARMState *s;
DriveInfo *dinfo;
- MemoryRegion *sdram = g_new(MemoryRegion, 1);
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
+
+ if (machine->ram_size != mc->default_ram_size) {
+ char *sz = size_to_str(mc->default_ram_size);
+ error_report("Invalid RAM size, should be %s", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
+ }
s = sa1110_init(machine->cpu_type);
- memory_region_allocate_system_memory(sdram, NULL, "strongarm.sdram",
- collie_binfo.ram_size);
- memory_region_add_subregion(get_system_memory(), SA_SDCS0, sdram);
+ memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram);
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000,
@@ -57,6 +63,8 @@ static void collie_machine_init(MachineClass *mc)
mc->init = collie_init;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("sa1110");
+ mc->default_ram_size = 0x20000000;
+ mc->default_ram_id = "strongarm.sdram";
}
DEFINE_MACHINE("collie", collie_machine_init)
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index 6dc2f1d..089f9a3 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -28,52 +28,42 @@ static struct arm_boot_info cubieboard_binfo = {
.board_id = 0x1008,
};
-typedef struct CubieBoardState {
- AwA10State *a10;
- MemoryRegion sdram;
-} CubieBoardState;
-
static void cubieboard_init(MachineState *machine)
{
- CubieBoardState *s = g_new(CubieBoardState, 1);
+ AwA10State *a10 = AW_A10(object_new(TYPE_AW_A10));
Error *err = NULL;
- s->a10 = AW_A10(object_new(TYPE_AW_A10));
-
- object_property_set_int(OBJECT(&s->a10->emac), 1, "phy-addr", &err);
+ object_property_set_int(OBJECT(&a10->emac), 1, "phy-addr", &err);
if (err != NULL) {
error_reportf_err(err, "Couldn't set phy address: ");
exit(1);
}
- object_property_set_int(OBJECT(&s->a10->timer), 32768, "clk0-freq", &err);
+ object_property_set_int(OBJECT(&a10->timer), 32768, "clk0-freq", &err);
if (err != NULL) {
error_reportf_err(err, "Couldn't set clk0 frequency: ");
exit(1);
}
- object_property_set_int(OBJECT(&s->a10->timer), 24000000, "clk1-freq",
- &err);
+ object_property_set_int(OBJECT(&a10->timer), 24000000, "clk1-freq", &err);
if (err != NULL) {
error_reportf_err(err, "Couldn't set clk1 frequency: ");
exit(1);
}
- object_property_set_bool(OBJECT(s->a10), true, "realized", &err);
+ object_property_set_bool(OBJECT(a10), true, "realized", &err);
if (err != NULL) {
error_reportf_err(err, "Couldn't realize Allwinner A10: ");
exit(1);
}
- memory_region_allocate_system_memory(&s->sdram, NULL, "cubieboard.ram",
- machine->ram_size);
memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
- &s->sdram);
+ machine->ram);
/* TODO create and connect IDE devices for ide_drive_get() */
cubieboard_binfo.ram_size = machine->ram_size;
- arm_load_kernel(&s->a10->cpu, machine, &cubieboard_binfo);
+ arm_load_kernel(&a10->cpu, machine, &cubieboard_binfo);
}
static void cubieboard_machine_init(MachineClass *mc)
@@ -84,6 +74,7 @@ static void cubieboard_machine_init(MachineClass *mc)
mc->block_default_type = IF_IDE;
mc->units_per_default_bus = 1;
mc->ignore_memory_transaction_failures = true;
+ mc->default_ram_id = "cubieboard.ram";
}
DEFINE_MACHINE("cubieboard", cubieboard_machine_init)
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index ef3fc2b..518a63e 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -35,39 +35,40 @@
#include "hw/loader.h"
#include "sysemu/sysemu.h"
#include "sysemu/qtest.h"
+#include "qemu/units.h"
+#include "qemu/cutils.h"
#define DIGIC4_ROM0_BASE 0xf0000000
#define DIGIC4_ROM1_BASE 0xf8000000
#define DIGIC4_ROM_MAX_SIZE 0x08000000
-typedef struct DigicBoardState {
- DigicState *digic;
- MemoryRegion ram;
-} DigicBoardState;
-
typedef struct DigicBoard {
- hwaddr ram_size;
- void (*add_rom0)(DigicBoardState *, hwaddr, const char *);
+ void (*add_rom0)(DigicState *, hwaddr, const char *);
const char *rom0_def_filename;
- void (*add_rom1)(DigicBoardState *, hwaddr, const char *);
+ void (*add_rom1)(DigicState *, hwaddr, const char *);
const char *rom1_def_filename;
} DigicBoard;
-static void digic4_board_init(DigicBoard *board)
+static void digic4_board_init(MachineState *machine, DigicBoard *board)
{
Error *err = NULL;
+ DigicState *s = DIGIC(object_new(TYPE_DIGIC));
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
+
+ if (machine->ram_size != mc->default_ram_size) {
+ char *sz = size_to_str(mc->default_ram_size);
+ error_report("Invalid RAM size, should be %s", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
+ }
- DigicBoardState *s = g_new(DigicBoardState, 1);
-
- s->digic = DIGIC(object_new(TYPE_DIGIC));
- object_property_set_bool(OBJECT(s->digic), true, "realized", &err);
+ object_property_set_bool(OBJECT(s), true, "realized", &err);
if (err != NULL) {
error_reportf_err(err, "Couldn't realize DIGIC SoC: ");
exit(1);
}
- memory_region_allocate_system_memory(&s->ram, NULL, "ram", board->ram_size);
- memory_region_add_subregion(get_system_memory(), 0, &s->ram);
+ memory_region_add_subregion(get_system_memory(), 0, machine->ram);
if (board->add_rom0) {
board->add_rom0(s, DIGIC4_ROM0_BASE, board->rom0_def_filename);
@@ -78,7 +79,7 @@ static void digic4_board_init(DigicBoard *board)
}
}
-static void digic_load_rom(DigicBoardState *s, hwaddr addr,
+static void digic_load_rom(DigicState *s, hwaddr addr,
hwaddr max_size, const char *def_filename)
{
target_long rom_size;
@@ -118,7 +119,7 @@ static void digic_load_rom(DigicBoardState *s, hwaddr addr,
* Samsung K8P3215UQB
* 64M Bit (4Mx16) Page Mode / Multi-Bank NOR Flash Memory
*/
-static void digic4_add_k8p3215uqb_rom(DigicBoardState *s, hwaddr addr,
+static void digic4_add_k8p3215uqb_rom(DigicState *s, hwaddr addr,
const char *def_filename)
{
#define FLASH_K8P3215UQB_SIZE (4 * 1024 * 1024)
@@ -135,14 +136,13 @@ static void digic4_add_k8p3215uqb_rom(DigicBoardState *s, hwaddr addr,
}
static DigicBoard digic4_board_canon_a1100 = {
- .ram_size = 64 * 1024 * 1024,
.add_rom1 = digic4_add_k8p3215uqb_rom,
.rom1_def_filename = "canon-a1100-rom1.bin",
};
static void canon_a1100_init(MachineState *machine)
{
- digic4_board_init(&digic4_board_canon_a1100);
+ digic4_board_init(machine, &digic4_board_canon_a1100);
}
static void canon_a1100_machine_init(MachineClass *mc)
@@ -150,6 +150,8 @@ static void canon_a1100_machine_init(MachineClass *mc)
mc->desc = "Canon PowerShot A1100 IS";
mc->init = &canon_a1100_init;
mc->ignore_memory_transaction_failures = true;
+ mc->default_ram_size = 64 * MiB;
+ mc->default_ram_id = "ram";
}
DEFINE_MACHINE("canon-a1100", canon_a1100_machine_init)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index 518d935..ac9de94 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -236,7 +236,6 @@ enum cxmachines {
*/
static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
{
- ram_addr_t ram_size = machine->ram_size;
DeviceState *dev = NULL;
SysBusDevice *busdev;
qemu_irq pic[128];
@@ -247,7 +246,6 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
qemu_irq cpu_virq[4];
qemu_irq cpu_vfiq[4];
MemoryRegion *sysram;
- MemoryRegion *dram;
MemoryRegion *sysmem;
char *sysboot_filename;
@@ -290,10 +288,8 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
}
sysmem = get_system_memory();
- dram = g_new(MemoryRegion, 1);
- memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
/* SDRAM at address zero. */
- memory_region_add_subregion(sysmem, 0, dram);
+ memory_region_add_subregion(sysmem, 0, machine->ram);
sysram = g_new(MemoryRegion, 1);
memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
@@ -387,7 +383,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
/* TODO create and connect IDE devices for ide_drive_get() */
- highbank_binfo.ram_size = ram_size;
+ highbank_binfo.ram_size = machine->ram_size;
/* highbank requires a dtb in order to boot, and the dtb will override
* the board ID. The following value is ignored, so set it to -1 to be
* clear that the value is meaningless.
@@ -430,6 +426,7 @@ static void highbank_class_init(ObjectClass *oc, void *data)
mc->units_per_default_bus = 1;
mc->max_cpus = 4;
mc->ignore_memory_transaction_failures = true;
+ mc->default_ram_id = "highbank.dram";
}
static const TypeInfo highbank_type = {
@@ -448,6 +445,7 @@ static void midway_class_init(ObjectClass *oc, void *data)
mc->units_per_default_bus = 1;
mc->max_cpus = 4;
mc->ignore_memory_transaction_failures = true;
+ mc->default_ram_id = "highbank.dram";
}
static const TypeInfo midway_type = {
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
index c76fc2b..26713d9 100644
--- a/hw/arm/imx25_pdk.c
+++ b/hw/arm/imx25_pdk.c
@@ -32,6 +32,7 @@
#include "exec/address-spaces.h"
#include "sysemu/qtest.h"
#include "hw/i2c/i2c.h"
+#include "qemu/cutils.h"
/* Memory map for PDK Emulation Baseboard:
* 0x00000000-0x7fffffff See i.MX25 SOC fr support
@@ -58,7 +59,6 @@
typedef struct IMX25PDK {
FslIMX25State soc;
- MemoryRegion ram;
MemoryRegion ram_alias;
} IMX25PDK;
@@ -66,6 +66,7 @@ static struct arm_boot_info imx25_pdk_binfo;
static void imx25_pdk_init(MachineState *machine)
{
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
IMX25PDK *s = g_new0(IMX25PDK, 1);
unsigned int ram_size;
unsigned int alias_offset;
@@ -78,16 +79,14 @@ static void imx25_pdk_init(MachineState *machine)
/* We need to initialize our memory */
if (machine->ram_size > (FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE)) {
- warn_report("RAM size " RAM_ADDR_FMT " above max supported, "
- "reduced to %x", machine->ram_size,
- FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE);
- machine->ram_size = FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE;
+ char *sz = size_to_str(mc->default_ram_size);
+ error_report("Invalid RAM size, should be %s", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
}
- memory_region_allocate_system_memory(&s->ram, NULL, "imx25.ram",
- machine->ram_size);
memory_region_add_subregion(get_system_memory(), FSL_IMX25_SDRAM0_ADDR,
- &s->ram);
+ machine->ram);
/* initialize the alias memory if any */
for (i = 0, ram_size = machine->ram_size, alias_offset = 0;
@@ -107,7 +106,8 @@ static void imx25_pdk_init(MachineState *machine)
if (size < ram[i].size) {
memory_region_init_alias(&s->ram_alias, NULL, "ram.alias",
- &s->ram, alias_offset, ram[i].size - size);
+ machine->ram,
+ alias_offset, ram[i].size - size);
memory_region_add_subregion(get_system_memory(),
ram[i].addr + size, &s->ram_alias);
}
@@ -135,6 +135,7 @@ static void imx25_pdk_machine_init(MachineClass *mc)
mc->desc = "ARM i.MX25 PDK board (ARM926)";
mc->init = imx25_pdk_init;
mc->ignore_memory_transaction_failures = true;
+ mc->default_ram_id = "imx25.ram";
}
DEFINE_MACHINE("imx25-pdk", imx25_pdk_machine_init)
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index 0cd94d9..cc845b8 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -585,7 +585,6 @@ static void integratorcp_init(MachineState *machine)
Object *cpuobj;
ARMCPU *cpu;
MemoryRegion *address_space_mem = get_system_memory();
- MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
qemu_irq pic[32];
DeviceState *dev, *sic, *icp;
@@ -605,14 +604,13 @@ static void integratorcp_init(MachineState *machine)
cpu = ARM_CPU(cpuobj);
- memory_region_allocate_system_memory(ram, NULL, "integrator.ram",
- ram_size);
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
/* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero*/
- memory_region_add_subregion(address_space_mem, 0, ram);
+ memory_region_add_subregion(address_space_mem, 0, machine->ram);
/* And again at address 0x80000000 */
- memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
+ memory_region_init_alias(ram_alias, NULL, "ram.alias", machine->ram,
+ 0, ram_size);
memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
dev = qdev_create(NULL, TYPE_INTEGRATOR_CM);
@@ -660,6 +658,7 @@ static void integratorcp_machine_init(MachineClass *mc)
mc->init = integratorcp_init;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
+ mc->default_ram_id = "integrator.ram";
}
DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
index 1d5ef28..34f6bcb 100644
--- a/hw/arm/kzm.c
+++ b/hw/arm/kzm.c
@@ -25,6 +25,7 @@
#include "hw/char/serial.h"
#include "sysemu/qtest.h"
#include "sysemu/sysemu.h"
+#include "qemu/cutils.h"
/* Memory map for Kzm Emulation Baseboard:
* 0x00000000-0x7fffffff See i.MX31 SOC for support
@@ -51,7 +52,6 @@
typedef struct IMX31KZM {
FslIMX31State soc;
- MemoryRegion ram;
MemoryRegion ram_alias;
} IMX31KZM;
@@ -78,16 +78,14 @@ static void kzm_init(MachineState *machine)
/* Check the amount of memory is compatible with the SOC */
if (machine->ram_size > (FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE)) {
- warn_report("RAM size " RAM_ADDR_FMT " above max supported, "
- "reduced to %x", machine->ram_size,
- FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE);
- machine->ram_size = FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE;
+ char *sz = size_to_str(FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE);
+ error_report("RAM size more than %s is not supported", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
}
- memory_region_allocate_system_memory(&s->ram, NULL, "kzm.ram",
- machine->ram_size);
memory_region_add_subregion(get_system_memory(), FSL_IMX31_SDRAM0_ADDR,
- &s->ram);
+ machine->ram);
/* initialize the alias memory if any */
for (i = 0, ram_size = machine->ram_size, alias_offset = 0;
@@ -107,7 +105,8 @@ static void kzm_init(MachineState *machine)
if (size < ram[i].size) {
memory_region_init_alias(&s->ram_alias, NULL, "ram.alias",
- &s->ram, alias_offset, ram[i].size - size);
+ machine->ram,
+ alias_offset, ram[i].size - size);
memory_region_add_subregion(get_system_memory(),
ram[i].addr + size, &s->ram_alias);
}
@@ -139,6 +138,7 @@ static void kzm_machine_init(MachineClass *mc)
mc->desc = "ARM KZM Emulation Baseboard (ARM1136)";
mc->init = kzm_init;
mc->ignore_memory_transaction_failures = true;
+ mc->default_ram_id = "kzm.ram";
}
DEFINE_MACHINE("kzm", kzm_machine_init)
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index e90b393..23a71ed 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -19,15 +19,10 @@
#include "qemu/error-report.h"
#include "sysemu/qtest.h"
-typedef struct {
- FslIMX6ULState soc;
- MemoryRegion ram;
-} MCIMX6ULEVK;
-
static void mcimx6ul_evk_init(MachineState *machine)
{
static struct arm_boot_info boot_info;
- MCIMX6ULEVK *s = g_new0(MCIMX6ULEVK, 1);
+ FslIMX6ULState *s;
int i;
if (machine->ram_size > FSL_IMX6UL_MMDC_SIZE) {
@@ -43,15 +38,12 @@ static void mcimx6ul_evk_init(MachineState *machine)
.nb_cpus = machine->smp.cpus,
};
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- TYPE_FSL_IMX6UL, &error_fatal, NULL);
-
- object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
+ s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL));
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(s), &error_fatal);
+ object_property_set_bool(OBJECT(s), true, "realized", &error_fatal);
- memory_region_allocate_system_memory(&s->ram, NULL, "mcimx6ul-evk.ram",
- machine->ram_size);
- memory_region_add_subregion(get_system_memory(),
- FSL_IMX6UL_MMDC_ADDR, &s->ram);
+ memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR,
+ machine->ram);
for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
BusState *bus;
@@ -61,7 +53,7 @@ static void mcimx6ul_evk_init(MachineState *machine)
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
- bus = qdev_get_child_bus(DEVICE(&s->soc.usdhc[i]), "sd-bus");
+ bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus");
carddev = qdev_create(bus, TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true,
@@ -69,7 +61,7 @@ static void mcimx6ul_evk_init(MachineState *machine)
}
if (!qtest_enabled()) {
- arm_load_kernel(&s->soc.cpu, machine, &boot_info);
+ arm_load_kernel(&s->cpu, machine, &boot_info);
}
}
@@ -78,5 +70,6 @@ static void mcimx6ul_evk_machine_init(MachineClass *mc)
mc->desc = "Freescale i.MX6UL Evaluation Kit (Cortex A7)";
mc->init = mcimx6ul_evk_init;
mc->max_cpus = FSL_IMX6UL_NUM_CPUS;
+ mc->default_ram_id = "mcimx6ul-evk.ram";
}
DEFINE_MACHINE("mcimx6ul-evk", mcimx6ul_evk_machine_init)
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index 0d1f62d..de1e264 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -21,15 +21,10 @@
#include "qemu/error-report.h"
#include "sysemu/qtest.h"
-typedef struct {
- FslIMX7State soc;
- MemoryRegion ram;
-} MCIMX7Sabre;
-
static void mcimx7d_sabre_init(MachineState *machine)
{
static struct arm_boot_info boot_info;
- MCIMX7Sabre *s = g_new0(MCIMX7Sabre, 1);
+ FslIMX7State *s;
int i;
if (machine->ram_size > FSL_IMX7_MMDC_SIZE) {
@@ -45,15 +40,12 @@ static void mcimx7d_sabre_init(MachineState *machine)
.nb_cpus = machine->smp.cpus,
};
- object_initialize_child(OBJECT(machine), "soc",
- &s->soc, sizeof(s->soc),
- TYPE_FSL_IMX7, &error_fatal, NULL);
- object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
+ s = FSL_IMX7(object_new(TYPE_FSL_IMX7));
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(s), &error_fatal);
+ object_property_set_bool(OBJECT(s), true, "realized", &error_fatal);
- memory_region_allocate_system_memory(&s->ram, NULL, "mcimx7d-sabre.ram",
- machine->ram_size);
- memory_region_add_subregion(get_system_memory(),
- FSL_IMX7_MMDC_ADDR, &s->ram);
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_MMDC_ADDR,
+ machine->ram);
for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
BusState *bus;
@@ -63,7 +55,7 @@ static void mcimx7d_sabre_init(MachineState *machine)
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
- bus = qdev_get_child_bus(DEVICE(&s->soc.usdhc[i]), "sd-bus");
+ bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus");
carddev = qdev_create(bus, TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true,
@@ -71,7 +63,7 @@ static void mcimx7d_sabre_init(MachineState *machine)
}
if (!qtest_enabled()) {
- arm_load_kernel(&s->soc.cpu[0], machine, &boot_info);
+ arm_load_kernel(&s->cpu[0], machine, &boot_info);
}
}
@@ -80,5 +72,6 @@ static void mcimx7d_sabre_machine_init(MachineClass *mc)
mc->desc = "Freescale i.MX7 DUAL SABRE (Cortex A7)";
mc->init = mcimx7d_sabre_init;
mc->max_cpus = FSL_IMX7_NUM_CPUS;
+ mc->default_ram_id = "mcimx7d-sabre.ram";
}
DEFINE_MACHINE("mcimx7d-sabre", mcimx7d_sabre_machine_init)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index f8b620b..a8dea7d 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -39,6 +39,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
+#include "qemu/cutils.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
@@ -79,7 +80,6 @@ typedef struct {
MachineState parent;
ARMSSE iotkit;
- MemoryRegion psram;
MemoryRegion ssram[3];
MemoryRegion ssram1_m;
MPS2SCC scc;
@@ -388,6 +388,13 @@ static void mps2tz_common_init(MachineState *machine)
exit(1);
}
+ if (machine->ram_size != mc->default_ram_size) {
+ char *sz = size_to_str(mc->default_ram_size);
+ error_report("Invalid RAM size, should be %s", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
+ }
+
sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit,
sizeof(mms->iotkit), mmc->armsse_type);
iotkitdev = DEVICE(&mms->iotkit);
@@ -458,9 +465,7 @@ static void mps2tz_common_init(MachineState *machine)
* tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
* call the 16MB our "system memory", as it's the largest lump.
*/
- memory_region_allocate_system_memory(&mms->psram,
- NULL, "mps.ram", 16 * MiB);
- memory_region_add_subregion(system_memory, 0x80000000, &mms->psram);
+ memory_region_add_subregion(system_memory, 0x80000000, machine->ram);
/* The overflow IRQs for all UARTs are ORed together.
* Tx, Rx and "combined" IRQs are sent to the NVIC separately.
@@ -642,6 +647,8 @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
mc->init = mps2tz_common_init;
iic->check = mps2_tz_idau_check;
+ mc->default_ram_size = 16 * MiB;
+ mc->default_ram_id = "mps.ram";
}
static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index d002b12..f246213 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
+#include "qemu/cutils.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
@@ -55,7 +56,6 @@ typedef struct {
MachineState parent;
ARMv7MState armv7m;
- MemoryRegion psram;
MemoryRegion ssram1;
MemoryRegion ssram1_m;
MemoryRegion ssram23;
@@ -118,6 +118,13 @@ static void mps2_common_init(MachineState *machine)
exit(1);
}
+ if (machine->ram_size != mc->default_ram_size) {
+ char *sz = size_to_str(mc->default_ram_size);
+ error_report("Invalid RAM size, should be %s", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
+ }
+
/* The FPGA images have an odd combination of different RAMs,
* because in hardware they are different implementations and
* connected to different buses, giving varying performance/size
@@ -146,9 +153,7 @@ static void mps2_common_init(MachineState *machine)
* This is of no use for QEMU so we don't implement it (as if
* zbt_boot_ctrl is always zero).
*/
- memory_region_allocate_system_memory(&mms->psram,
- NULL, "mps.ram", 16 * MiB);
- memory_region_add_subregion(system_memory, 0x21000000, &mms->psram);
+ memory_region_add_subregion(system_memory, 0x21000000, machine->ram);
switch (mmc->fpga_type) {
case FPGA_AN385:
@@ -338,6 +343,8 @@ static void mps2_class_init(ObjectClass *oc, void *data)
mc->init = mps2_common_init;
mc->max_cpus = 1;
+ mc->default_ram_size = 16 * MiB;
+ mc->default_ram_id = "mps.ram";
}
static void mps2_an385_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index dc551bb..db8b03c 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -32,6 +32,7 @@
#include "sysemu/runstate.h"
#include "exec/address-spaces.h"
#include "ui/pixel_ops.h"
+#include "qemu/cutils.h"
#define MP_MISC_BASE 0x80002000
#define MP_MISC_SIZE 0x00001000
@@ -1589,16 +1590,21 @@ static void musicpal_init(MachineState *machine)
int i;
unsigned long flash_size;
DriveInfo *dinfo;
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
MemoryRegion *address_space_mem = get_system_memory();
- MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
+ /* For now we use a fixed - the original - RAM size */
+ if (machine->ram_size != mc->default_ram_size) {
+ char *sz = size_to_str(mc->default_ram_size);
+ error_report("Invalid RAM size, should be %s", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
+ }
+
cpu = ARM_CPU(cpu_create(machine->cpu_type));
- /* For now we use a fixed - the original - RAM size */
- memory_region_allocate_system_memory(ram, NULL, "musicpal.ram",
- MP_RAM_DEFAULT_SIZE);
- memory_region_add_subregion(address_space_mem, 0, ram);
+ memory_region_add_subregion(address_space_mem, 0, machine->ram);
memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE,
&error_fatal);
@@ -1714,6 +1720,8 @@ static void musicpal_machine_init(MachineClass *mc)
mc->init = musicpal_init;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
+ mc->default_ram_size = MP_RAM_DEFAULT_SIZE;
+ mc->default_ram_id = "musicpal.ram";
}
DEFINE_MACHINE("musicpal", musicpal_machine_init)
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index 3fd196f..eae800b 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -47,7 +47,6 @@
/* Nokia N8x0 support */
struct n800_s {
- MemoryRegion sdram;
struct omap_mpu_state_s *mpu;
struct rfbi_chip_s blizzard;
@@ -1311,13 +1310,19 @@ static void n8x0_init(MachineState *machine,
struct arm_boot_info *binfo, int model)
{
struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
- uint64_t sdram_size = binfo->ram_size;
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
- memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram",
- sdram_size);
- memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE, &s->sdram);
+ if (machine->ram_size != mc->default_ram_size) {
+ char *sz = size_to_str(mc->default_ram_size);
+ error_report("Invalid RAM size, should be %s", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
+ }
+
+ memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE,
+ machine->ram);
- s->mpu = omap2420_mpu_init(&s->sdram, machine->cpu_type);
+ s->mpu = omap2420_mpu_init(machine->ram, machine->cpu_type);
/* Setup peripherals
*
@@ -1383,9 +1388,8 @@ static void n8x0_init(MachineState *machine,
*
* The code above is for loading the `zImage' file from Nokia
* images. */
- load_image_targphys(option_rom[0].name,
- OMAP2_Q2_BASE + 0x400000,
- sdram_size - 0x400000);
+ load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000,
+ machine->ram_size - 0x400000);
n800_setup_nolo_tags(nolo_tags);
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
@@ -1395,16 +1399,12 @@ static void n8x0_init(MachineState *machine,
static struct arm_boot_info n800_binfo = {
.loader_start = OMAP2_Q2_BASE,
- /* Actually two chips of 0x4000000 bytes each */
- .ram_size = 0x08000000,
.board_id = 0x4f7,
.atag_board = n800_atag_setup,
};
static struct arm_boot_info n810_binfo = {
.loader_start = OMAP2_Q2_BASE,
- /* Actually two chips of 0x4000000 bytes each */
- .ram_size = 0x08000000,
/* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
* used by some older versions of the bootloader and 5555 is used
* instead (including versions that shipped with many devices). */
@@ -1431,6 +1431,9 @@ static void n800_class_init(ObjectClass *oc, void *data)
mc->default_boot_order = "";
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2");
+ /* Actually two chips of 0x4000000 bytes each */
+ mc->default_ram_size = 0x08000000;
+ mc->default_ram_id = "omap2.dram";
}
static const TypeInfo n800_type = {
@@ -1448,6 +1451,9 @@ static void n810_class_init(ObjectClass *oc, void *data)
mc->default_boot_order = "";
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2");
+ /* Actually two chips of 0x4000000 bytes each */
+ mc->default_ram_size = 0x08000000;
+ mc->default_ram_id = "omap2.dram";
}
static const TypeInfo n810_type = {
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index be24571..2bebab4 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -35,6 +35,7 @@
#include "sysemu/qtest.h"
#include "exec/address-spaces.h"
#include "cpu.h"
+#include "qemu/cutils.h"
/*****************************************************************************/
/* Siemens SX1 Cellphone V1 */
@@ -102,8 +103,8 @@ static struct arm_boot_info sx1_binfo = {
static void sx1_init(MachineState *machine, const int version)
{
struct omap_mpu_state_s *mpu;
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
MemoryRegion *address_space = get_system_memory();
- MemoryRegion *dram = g_new(MemoryRegion, 1);
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *cs = g_new(MemoryRegion, 4);
static uint32_t cs0val = 0x00213090;
@@ -115,15 +116,20 @@ static void sx1_init(MachineState *machine, const int version)
uint32_t flash_size = flash0_size;
int be;
+ if (machine->ram_size != mc->default_ram_size) {
+ char *sz = size_to_str(mc->default_ram_size);
+ error_report("Invalid RAM size, should be %s", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
+ }
+
if (version == 2) {
flash_size = flash2_size;
}
- memory_region_allocate_system_memory(dram, NULL, "omap1.dram",
- sx1_binfo.ram_size);
- memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, dram);
+ memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, machine->ram);
- mpu = omap310_mpu_init(dram, machine->cpu_type);
+ mpu = omap310_mpu_init(machine->ram, machine->cpu_type);
/* External Flash (EMIFS) */
memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size,
@@ -223,6 +229,8 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
mc->init = sx1_init_v2;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
+ mc->default_ram_size = sdram_size;
+ mc->default_ram_id = "omap1.dram";
}
static const TypeInfo sx1_machine_v2_type = {
@@ -239,6 +247,8 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
mc->init = sx1_init_v1;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
+ mc->default_ram_size = sdram_size;
+ mc->default_ram_id = "omap1.dram";
}
static const TypeInfo sx1_machine_v1_type = {
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index 72eca8c..99554bd 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -31,6 +31,7 @@
#include "hw/loader.h"
#include "exec/address-spaces.h"
#include "cpu.h"
+#include "qemu/cutils.h"
static uint64_t static_read(void *opaque, hwaddr offset, unsigned size)
{
@@ -195,15 +196,21 @@ static void palmte_init(MachineState *machine)
static uint32_t cs2val = 0x0000e1a0;
static uint32_t cs3val = 0xe1a0e1a0;
int rom_size, rom_loaded = 0;
- MemoryRegion *dram = g_new(MemoryRegion, 1);
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *cs = g_new(MemoryRegion, 4);
- memory_region_allocate_system_memory(dram, NULL, "omap1.dram",
- palmte_binfo.ram_size);
- memory_region_add_subregion(address_space_mem, OMAP_EMIFF_BASE, dram);
+ if (machine->ram_size != mc->default_ram_size) {
+ char *sz = size_to_str(mc->default_ram_size);
+ error_report("Invalid RAM size, should be %s", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
+ }
+
+ memory_region_add_subregion(address_space_mem, OMAP_EMIFF_BASE,
+ machine->ram);
- mpu = omap310_mpu_init(dram, machine->cpu_type);
+ mpu = omap310_mpu_init(machine->ram, machine->cpu_type);
/* External Flash (EMIFS) */
memory_region_init_ram(flash, NULL, "palmte.flash", flash_size,
@@ -265,6 +272,8 @@ static void palmte_machine_init(MachineClass *mc)
mc->init = palmte_init;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
+ mc->default_ram_size = 0x02000000;
+ mc->default_ram_id = "omap1.dram";
}
DEFINE_MACHINE("cheetah", palmte_machine_init)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 90ad9b8..acd2bb7 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -39,7 +39,6 @@ typedef struct RaspiMachineState {
MachineState parent_obj;
/*< public >*/
BCM283XState soc;
- MemoryRegion ram;
} RaspiMachineState;
typedef struct RaspiMachineClass {
@@ -277,16 +276,14 @@ static void raspi_machine_init(MachineState *machine)
exit(1);
}
- /* Allocate and map RAM */
- memory_region_allocate_system_memory(&s->ram, OBJECT(machine), "ram",
- machine->ram_size);
/* FIXME: Remove when we have custom CPU address space support */
- memory_region_add_subregion_overlap(get_system_memory(), 0, &s->ram, 0);
+ memory_region_add_subregion_overlap(get_system_memory(), 0,
+ machine->ram, 0);
/* Setup the SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
board_soc_type(board_rev), &error_abort, NULL);
- object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
+ object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram),
&error_abort);
object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev",
&error_abort);
@@ -324,6 +321,7 @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
mc->no_cdrom = 1;
mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev);
mc->default_ram_size = board_ram_size(board_rev);
+ mc->default_ram_id = "ram";
if (board_version(board_rev) == 2) {
mc->ignore_memory_transaction_failures = true;
}
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
index 96cc455..e31694b 100644
--- a/hw/arm/sabrelite.c
+++ b/hw/arm/sabrelite.c
@@ -19,11 +19,6 @@
#include "qemu/error-report.h"
#include "sysemu/qtest.h"
-typedef struct IMX6Sabrelite {
- FslIMX6State soc;
- MemoryRegion ram;
-} IMX6Sabrelite;
-
static struct arm_boot_info sabrelite_binfo = {
/* DDR memory start */
.loader_start = FSL_IMX6_MMDC_ADDR,
@@ -45,7 +40,7 @@ static void sabrelite_reset_secondary(ARMCPU *cpu,
static void sabrelite_init(MachineState *machine)
{
- IMX6Sabrelite *s = g_new0(IMX6Sabrelite, 1);
+ FslIMX6State *s;
Error *err = NULL;
/* Check the amount of memory is compatible with the SOC */
@@ -55,19 +50,16 @@ static void sabrelite_init(MachineState *machine)
exit(1);
}
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- TYPE_FSL_IMX6, &error_abort, NULL);
-
- object_property_set_bool(OBJECT(&s->soc), true, "realized", &err);
+ s = FSL_IMX6(object_new(TYPE_FSL_IMX6));
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(s), &error_fatal);
+ object_property_set_bool(OBJECT(s), true, "realized", &err);
if (err != NULL) {
error_report("%s", error_get_pretty(err));
exit(1);
}
- memory_region_allocate_system_memory(&s->ram, NULL, "sabrelite.ram",
- machine->ram_size);
memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR,
- &s->ram);
+ machine->ram);
{
/*
@@ -78,7 +70,7 @@ static void sabrelite_init(MachineState *machine)
/* Add the sst25vf016b NOR FLASH memory to first SPI */
Object *spi_dev;
- spi_dev = object_resolve_path_component(OBJECT(&s->soc), "spi1");
+ spi_dev = object_resolve_path_component(OBJECT(s), "spi1");
if (spi_dev) {
SSIBus *spi_bus;
@@ -109,7 +101,7 @@ static void sabrelite_init(MachineState *machine)
sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary;
if (!qtest_enabled()) {
- arm_load_kernel(&s->soc.cpu[0], machine, &sabrelite_binfo);
+ arm_load_kernel(&s->cpu[0], machine, &sabrelite_binfo);
}
}
@@ -119,6 +111,7 @@ static void sabrelite_machine_init(MachineClass *mc)
mc->init = sabrelite_init;
mc->max_cpus = FSL_IMX6_NUM_CPUS;
mc->ignore_memory_transaction_failures = true;
+ mc->default_ram_id = "sabrelite.ram";
}
DEFINE_MACHINE("sabrelite", sabrelite_machine_init)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 9b5bcb5..1cba9fc 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -593,7 +593,6 @@ static void sbsa_ref_init(MachineState *machine)
MachineClass *mc = MACHINE_GET_CLASS(machine);
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1);
- MemoryRegion *ram = g_new(MemoryRegion, 1);
bool firmware_loaded;
const CPUArchIdList *possible_cpus;
int n, sbsa_max_cpus;
@@ -685,9 +684,8 @@ static void sbsa_ref_init(MachineState *machine)
object_unref(cpuobj);
}
- memory_region_allocate_system_memory(ram, NULL, "sbsa-ref.ram",
- machine->ram_size);
- memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ram);
+ memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base,
+ machine->ram);
create_fdt(sms);
@@ -785,6 +783,7 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data)
mc->block_default_type = IF_IDE;
mc->no_cdrom = 1;
mc->default_ram_size = 1 * GiB;
+ mc->default_ram_id = "sbsa-ref.ram";
mc->default_cpus = 4;
mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids;
mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props;
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index 23eb117..0f2573f 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -74,8 +74,7 @@ static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte,
dma_addr_t addr = baseaddr + index * sizeof(*pte);
/* TODO: guarantee 64-bit single-copy atomicity */
- ret = dma_memory_read(&address_space_memory, addr,
- (uint8_t *)pte, sizeof(*pte));
+ ret = dma_memory_read(&address_space_memory, addr, pte, sizeof(*pte));
if (ret != MEMTX_OK) {
info->type = SMMU_PTW_ERR_WALK_EABT;
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 8b5f157..57a79df 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -279,8 +279,7 @@ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
trace_smmuv3_get_ste(addr);
/* TODO: guarantee 64-bit single-copy atomicity */
- ret = dma_memory_read(&address_space_memory, addr,
- (void *)buf, sizeof(*buf));
+ ret = dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf));
if (ret != MEMTX_OK) {
qemu_log_mask(LOG_GUEST_ERROR,
"Cannot fetch pte at address=0x%"PRIx64"\n", addr);
@@ -301,8 +300,7 @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid,
trace_smmuv3_get_cd(addr);
/* TODO: guarantee 64-bit single-copy atomicity */
- ret = dma_memory_read(&address_space_memory, addr,
- (void *)buf, sizeof(*buf));
+ ret = dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf));
if (ret != MEMTX_OK) {
qemu_log_mask(LOG_GUEST_ERROR,
"Cannot fetch pte at address=0x%"PRIx64"\n", addr);
@@ -406,8 +404,8 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste,
l2_ste_offset = sid & ((1 << s->sid_split) - 1);
l1ptr = (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std));
/* TODO: guarantee 64-bit single-copy atomicity */
- ret = dma_memory_read(&address_space_memory, l1ptr,
- (uint8_t *)&l1std, sizeof(l1std));
+ ret = dma_memory_read(&address_space_memory, l1ptr, &l1std,
+ sizeof(l1std));
if (ret != MEMTX_OK) {
qemu_log_mask(LOG_GUEST_ERROR,
"Could not read L1PTR at 0X%"PRIx64"\n", l1ptr);
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index e86af01..f3c4a50 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -184,7 +184,6 @@ static void versatile_init(MachineState *machine, int board_id)
Object *cpuobj;
ARMCPU *cpu;
MemoryRegion *sysmem = get_system_memory();
- MemoryRegion *ram = g_new(MemoryRegion, 1);
qemu_irq pic[32];
qemu_irq sic[32];
DeviceState *dev, *sysctl;
@@ -220,11 +219,9 @@ static void versatile_init(MachineState *machine, int board_id)
cpu = ARM_CPU(cpuobj);
- memory_region_allocate_system_memory(ram, NULL, "versatile.ram",
- machine->ram_size);
/* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero. */
- memory_region_add_subregion(sysmem, 0, ram);
+ memory_region_add_subregion(sysmem, 0, machine->ram);
sysctl = qdev_create(NULL, "realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
@@ -398,6 +395,7 @@ static void versatilepb_class_init(ObjectClass *oc, void *data)
mc->block_default_type = IF_SCSI;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
+ mc->default_ram_id = "versatile.ram";
}
static const TypeInfo versatilepb_type = {
@@ -415,6 +413,7 @@ static void versatileab_class_init(ObjectClass *oc, void *data)
mc->block_default_type = IF_SCSI;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
+ mc->default_ram_id = "versatile.ram";
}
static const TypeInfo versatileab_type = {
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 4673a88..ed683ee 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -273,7 +273,6 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,
{
MachineState *machine = MACHINE(vms);
MemoryRegion *sysmem = get_system_memory();
- MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *lowram = g_new(MemoryRegion, 1);
ram_addr_t low_ram_size;
@@ -283,8 +282,6 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,
exit(1);
}
- memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem",
- ram_size);
low_ram_size = ram_size;
if (low_ram_size > 0x4000000) {
low_ram_size = 0x4000000;
@@ -293,9 +290,10 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,
* address space should in theory be remappable to various
* things including ROM or RAM; we always map the RAM there.
*/
- memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size);
+ memory_region_init_alias(lowram, NULL, "vexpress.lowmem", machine->ram,
+ 0, low_ram_size);
memory_region_add_subregion(sysmem, 0x0, lowram);
- memory_region_add_subregion(sysmem, 0x60000000, ram);
+ memory_region_add_subregion(sysmem, 0x60000000, machine->ram);
/* 0x1e000000 A9MPCore (SCU) private memory region */
init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic,
@@ -360,7 +358,6 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,
{
MachineState *machine = MACHINE(vms);
MemoryRegion *sysmem = get_system_memory();
- MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
{
@@ -375,10 +372,8 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,
}
}
- memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem",
- ram_size);
/* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
- memory_region_add_subregion(sysmem, 0x80000000, ram);
+ memory_region_add_subregion(sysmem, 0x80000000, machine->ram);
/* 0x2c000000 A15MPCore private memory region (GIC) */
init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV,
@@ -795,6 +790,7 @@ static void vexpress_class_init(ObjectClass *oc, void *data)
mc->init = vexpress_common_init;
mc->max_cpus = 4;
mc->ignore_memory_transaction_failures = true;
+ mc->default_ram_id = "vexpress.highmem";
}
static void vexpress_a9_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index f788fe2..e591a12 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1512,7 +1512,6 @@ static void machvirt_init(MachineState *machine)
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *secure_sysmem = NULL;
int n, virt_max_cpus;
- MemoryRegion *ram = g_new(MemoryRegion, 1);
bool firmware_loaded;
bool aarch64 = true;
bool has_ged = !vmc->no_ged;
@@ -1706,9 +1705,8 @@ static void machvirt_init(MachineState *machine)
}
}
- memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",
- machine->ram_size);
- memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram);
+ memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
+ machine->ram);
if (machine->device_memory) {
memory_region_add_subregion(sysmem, machine->device_memory->base,
&machine->device_memory->mr);
@@ -2058,6 +2056,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
hc->unplug_request = virt_machine_device_unplug_request_cb;
mc->numa_mem_supported = true;
mc->auto_enable_numa_with_memhp = true;
+ mc->default_ram_id = "mach-virt.ram";
}
static void virt_instance_init(Object *obj)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 3a0fa5b..3d439a4 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -158,16 +158,20 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
static void zynq_init(MachineState *machine)
{
- ram_addr_t ram_size = machine->ram_size;
ARMCPU *cpu;
MemoryRegion *address_space_mem = get_system_memory();
- MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
DeviceState *dev;
SysBusDevice *busdev;
qemu_irq pic[64];
int n;
+ /* max 2GB ram */
+ if (machine->ram_size > 2 * GiB) {
+ error_report("RAM size more than 2 GiB is not supported");
+ exit(EXIT_FAILURE);
+ }
+
cpu = ARM_CPU(object_new(machine->cpu_type));
/* By default A9 CPUs have EL3 enabled. This board does not
@@ -184,15 +188,8 @@ static void zynq_init(MachineState *machine)
&error_fatal);
object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
- /* max 2GB ram */
- if (ram_size > 0x80000000) {
- ram_size = 0x80000000;
- }
-
/* DDR remapped to address zero. */
- memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
- ram_size);
- memory_region_add_subregion(address_space_mem, 0, ext_ram);
+ memory_region_add_subregion(address_space_mem, 0, machine->ram);
/* 256K of on-chip memory */
memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB,
@@ -300,7 +297,7 @@ static void zynq_init(MachineState *machine)
sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
sysbus_mmio_map(busdev, 0, 0xF8007000);
- zynq_binfo.ram_size = ram_size;
+ zynq_binfo.ram_size = machine->ram_size;
zynq_binfo.nb_cpus = 1;
zynq_binfo.board_id = 0xd32;
zynq_binfo.loader_start = 0;
@@ -318,6 +315,7 @@ static void zynq_machine_init(MachineClass *mc)
mc->no_sdcard = 1;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
+ mc->default_ram_id = "zynq.ext_ram";
}
DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 0d2e3bd..e7f4ca8 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -30,7 +30,6 @@ typedef struct VersalVirt {
MachineState parent_obj;
Versal soc;
- MemoryRegion mr_ddr;
void *fdt;
int fdt_size;
@@ -414,12 +413,9 @@ static void versal_virt_init(MachineState *machine)
psci_conduit = QEMU_PSCI_CONDUIT_SMC;
}
- memory_region_allocate_system_memory(&s->mr_ddr, NULL, "ddr",
- machine->ram_size);
-
sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc,
sizeof(s->soc), TYPE_XLNX_VERSAL);
- object_property_set_link(OBJECT(&s->soc), OBJECT(&s->mr_ddr),
+ object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
"ddr", &error_abort);
object_property_set_int(OBJECT(&s->soc), psci_conduit,
"psci-conduit", &error_abort);
@@ -473,6 +469,7 @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
mc->no_cdrom = true;
+ mc->default_ram_id = "ddr";
}
static const TypeInfo versal_virt_machine_init_typeinfo = {
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index 53cfe7c..bd645ad 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -28,7 +28,6 @@ typedef struct XlnxZCU102 {
MachineState parent_obj;
XlnxZynqMPState soc;
- MemoryRegion ddr_ram;
bool secure;
bool virt;
@@ -87,13 +86,10 @@ static void xlnx_zcu102_init(MachineState *machine)
ram_size);
}
- memory_region_allocate_system_memory(&s->ddr_ram, NULL, "ddr-ram",
- ram_size);
-
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
TYPE_XLNX_ZYNQMP, &error_abort, NULL);
- object_property_set_link(OBJECT(&s->soc), OBJECT(&s->ddr_ram),
+ object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
"ddr-ram", &error_abort);
object_property_set_bool(OBJECT(&s->soc), s->secure, "secure",
&error_fatal);
@@ -211,6 +207,7 @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
mc->ignore_memory_transaction_failures = true;
mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS;
+ mc->default_ram_id = "ddr-ram";
}
static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
generated by cgit v1.1 at 2024-11-18 06:03:18 +0000