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-rw-r--r--hw/arm/Kconfig9
-rw-r--r--hw/arm/allwinner-a10.c40
-rw-r--r--hw/arm/allwinner-h3.c11
-rw-r--r--hw/arm/bcm2836.c9
-rw-r--r--hw/arm/collie.c25
-rw-r--r--hw/arm/cubieboard.c11
-rw-r--r--hw/arm/gumstix.c45
-rw-r--r--hw/arm/mainstone.c37
-rw-r--r--hw/arm/meson.build1
-rw-r--r--hw/arm/musicpal.c9
-rw-r--r--hw/arm/olimex-stm32-h405.c69
-rw-r--r--hw/arm/omap1.c115
-rw-r--r--hw/arm/omap2.c40
-rw-r--r--hw/arm/omap_sx1.c55
-rw-r--r--hw/arm/palm.c2
-rw-r--r--hw/arm/pxa2xx.c8
-rw-r--r--hw/arm/spitz.c6
-rw-r--r--hw/arm/stellaris.c73
-rw-r--r--hw/arm/stm32f405_soc.c8
-rw-r--r--hw/arm/tosa.c2
-rw-r--r--hw/arm/versatilepb.c6
-rw-r--r--hw/arm/vexpress.c10
-rw-r--r--hw/arm/z2.c16
23 files changed, 358 insertions, 249 deletions
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 17fcde8..19d6b9d 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -119,6 +119,10 @@ config NETDUINOPLUS2
bool
select STM32F405_SOC
+config OLIMEX_STM32_H405
+ bool
+ select STM32F405_SOC
+
config NSERIES
bool
select OMAP
@@ -319,7 +323,11 @@ config ALLWINNER_A10
select AHCI
select ALLWINNER_A10_PIT
select ALLWINNER_A10_PIC
+ select ALLWINNER_A10_CCM
+ select ALLWINNER_A10_DRAMC
select ALLWINNER_EMAC
+ select ALLWINNER_I2C
+ select AXP209_PMU
select SERIAL
select UNIMP
@@ -327,6 +335,7 @@ config ALLWINNER_H3
bool
select ALLWINNER_A10_PIT
select ALLWINNER_SUN8I_EMAC
+ select ALLWINNER_I2C
select SERIAL
select ARM_TIMER
select ARM_GIC
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index 7908228..dc1966f 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -24,8 +24,12 @@
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "hw/usb/hcd-ohci.h"
+#include "hw/loader.h"
+#define AW_A10_SRAM_A_BASE 0x00000000
+#define AW_A10_DRAMC_BASE 0x01c01000
#define AW_A10_MMC0_BASE 0x01c0f000
+#define AW_A10_CCM_BASE 0x01c20000
#define AW_A10_PIC_REG_BASE 0x01c20400
#define AW_A10_PIT_REG_BASE 0x01c20c00
#define AW_A10_UART0_REG_BASE 0x01c28000
@@ -34,6 +38,23 @@
#define AW_A10_OHCI_BASE 0x01c14400
#define AW_A10_SATA_BASE 0x01c18000
#define AW_A10_RTC_BASE 0x01c20d00
+#define AW_A10_I2C0_BASE 0x01c2ac00
+
+void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk)
+{
+ const int64_t rom_size = 32 * KiB;
+ g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
+
+ if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
+ error_setg(&error_fatal, "%s: failed to read BlockBackend data",
+ __func__);
+ return;
+ }
+
+ rom_add_blob("allwinner-a10.bootrom", buffer, rom_size,
+ rom_size, AW_A10_SRAM_A_BASE,
+ NULL, NULL, NULL, NULL, false);
+}
static void aw_a10_init(Object *obj)
{
@@ -46,10 +67,16 @@ static void aw_a10_init(Object *obj)
object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
+ object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
+
+ object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_A10_DRAMC);
+
object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
+ object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C);
+
if (machine_usb(current_machine)) {
int i;
@@ -103,6 +130,14 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
+ /* Clock Control Module */
+ sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
+
+ /* DRAM Control Module */
+ sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, AW_A10_DRAMC_BASE);
+
/* FIXME use qdev NIC properties instead of nd_table[] */
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
@@ -162,6 +197,11 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
/* RTC */
sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
+
+ /* I2C */
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7));
}
static void aw_a10_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 308ed15..bfce3c8 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -53,6 +53,7 @@ const hwaddr allwinner_h3_memmap[] = {
[AW_H3_DEV_UART1] = 0x01c28400,
[AW_H3_DEV_UART2] = 0x01c28800,
[AW_H3_DEV_UART3] = 0x01c28c00,
+ [AW_H3_DEV_TWI0] = 0x01c2ac00,
[AW_H3_DEV_EMAC] = 0x01c30000,
[AW_H3_DEV_DRAMCOM] = 0x01c62000,
[AW_H3_DEV_DRAMCTL] = 0x01c63000,
@@ -106,7 +107,6 @@ struct AwH3Unimplemented {
{ "uart1", 0x01c28400, 1 * KiB },
{ "uart2", 0x01c28800, 1 * KiB },
{ "uart3", 0x01c28c00, 1 * KiB },
- { "twi0", 0x01c2ac00, 1 * KiB },
{ "twi1", 0x01c2b000, 1 * KiB },
{ "twi2", 0x01c2b400, 1 * KiB },
{ "scr", 0x01c2c400, 1 * KiB },
@@ -150,6 +150,7 @@ enum {
AW_H3_GIC_SPI_UART1 = 1,
AW_H3_GIC_SPI_UART2 = 2,
AW_H3_GIC_SPI_UART3 = 3,
+ AW_H3_GIC_SPI_TWI0 = 6,
AW_H3_GIC_SPI_TIMER0 = 18,
AW_H3_GIC_SPI_TIMER1 = 19,
AW_H3_GIC_SPI_MMC0 = 60,
@@ -225,6 +226,8 @@ static void allwinner_h3_init(Object *obj)
"ram-size");
object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
+
+ object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C);
}
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -423,6 +426,12 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]);
+ /* I2C */
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_H3_DEV_TWI0]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
+
/* Unimplemented devices */
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
create_unimplemented_device(unimplemented[i].device_name,
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index 2435433..f894338 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -16,7 +16,7 @@
#include "hw/arm/raspi_platform.h"
#include "hw/sysbus.h"
-typedef struct BCM283XClass {
+struct BCM283XClass {
/*< private >*/
DeviceClass parent_class;
/*< public >*/
@@ -26,12 +26,7 @@ typedef struct BCM283XClass {
hwaddr peri_base; /* Peripheral base address seen by the CPU */
hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
int clusterid;
-} BCM283XClass;
-
-#define BCM283X_CLASS(klass) \
- OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
-#define BCM283X_GET_CLASS(obj) \
- OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
+};
static Property bcm2836_enabled_cores_property =
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index 8df31e2..9edff59 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -20,6 +20,10 @@
#include "cpu.h"
#include "qom/object.h"
+#define RAM_SIZE (512 * MiB)
+#define FLASH_SIZE (32 * MiB)
+#define FLASH_SECTOR_SIZE (64 * KiB)
+
struct CollieMachineState {
MachineState parent;
@@ -31,12 +35,11 @@ OBJECT_DECLARE_SIMPLE_TYPE(CollieMachineState, COLLIE_MACHINE)
static struct arm_boot_info collie_binfo = {
.loader_start = SA_SDCS0,
- .ram_size = 0x20000000,
+ .ram_size = RAM_SIZE,
};
static void collie_init(MachineState *machine)
{
- DriveInfo *dinfo;
MachineClass *mc = MACHINE_GET_CLASS(machine);
CollieMachineState *cms = COLLIE_MACHINE(machine);
@@ -51,15 +54,13 @@ static void collie_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram);
- dinfo = drive_get(IF_PFLASH, 0, 0);
- pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000,
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
- 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0);
-
- dinfo = drive_get(IF_PFLASH, 0, 1);
- pflash_cfi01_register(SA_CS1, "collie.fl2", 0x02000000,
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
- 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0);
+ for (unsigned i = 0; i < 2; i++) {
+ DriveInfo *dinfo = drive_get(IF_PFLASH, 0, i);
+ pflash_cfi01_register(i ? SA_CS1 : SA_CS0,
+ i ? "collie.fl2" : "collie.fl1", FLASH_SIZE,
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+ FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
+ }
sysbus_create_simple("scoop", 0x40800000, NULL);
@@ -75,7 +76,7 @@ static void collie_machine_class_init(ObjectClass *oc, void *data)
mc->init = collie_init;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("sa1110");
- mc->default_ram_size = 0x20000000;
+ mc->default_ram_size = RAM_SIZE;
mc->default_ram_id = "strongarm.sdram";
}
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index 5e3372a..71a7df1 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -20,6 +20,7 @@
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "hw/arm/allwinner-a10.h"
+#include "hw/i2c/i2c.h"
static struct arm_boot_info cubieboard_binfo = {
.loader_start = AW_A10_SDRAM_BASE,
@@ -34,6 +35,7 @@ static void cubieboard_init(MachineState *machine)
BlockBackend *blk;
BusState *bus;
DeviceState *carddev;
+ I2CBus *i2c;
/* BIOS is not supported by this board */
if (machine->firmware) {
@@ -80,6 +82,10 @@ static void cubieboard_init(MachineState *machine)
exit(1);
}
+ /* Connect AXP 209 */
+ i2c = I2C_BUS(qdev_get_child_bus(DEVICE(&a10->i2c0), "i2c"));
+ i2c_slave_create_simple(i2c, "axp209_pmu", 0x34);
+
/* Retrieve SD bus */
di = drive_get(IF_SD, 0, 0);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
@@ -93,6 +99,11 @@ static void cubieboard_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
machine->ram);
+ /* Load target kernel or start using BootROM */
+ if (!machine->kernel_filename && blk && blk_is_available(blk)) {
+ /* Use Boot ROM to copy data from SD card to SRAM */
+ allwinner_a10_bootrom_setup(a10, blk);
+ }
/* TODO create and connect IDE devices for ide_drive_get() */
cubieboard_binfo.ram_size = machine->ram_size;
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
index 3a4bc33..2ca4140 100644
--- a/hw/arm/gumstix.c
+++ b/hw/arm/gumstix.c
@@ -10,7 +10,7 @@
* Contributions after 2012-01-13 are licensed under the terms of the
* GNU GPL, version 2 or (at your option) any later version.
*/
-
+
/*
* Example usage:
*
@@ -35,6 +35,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "qemu/error-report.h"
#include "hw/arm/pxa.h"
#include "net/net.h"
@@ -45,18 +46,20 @@
#include "sysemu/qtest.h"
#include "cpu.h"
-static const int sector_len = 128 * 1024;
+#define CONNEX_FLASH_SIZE (16 * MiB)
+#define CONNEX_RAM_SIZE (64 * MiB)
+
+#define VERDEX_FLASH_SIZE (32 * MiB)
+#define VERDEX_RAM_SIZE (256 * MiB)
+
+#define FLASH_SECTOR_SIZE (128 * KiB)
static void connex_init(MachineState *machine)
{
PXA2xxState *cpu;
DriveInfo *dinfo;
- MemoryRegion *address_space_mem = get_system_memory();
- uint32_t connex_rom = 0x01000000;
- uint32_t connex_ram = 0x04000000;
-
- cpu = pxa255_init(address_space_mem, connex_ram);
+ cpu = pxa255_init(CONNEX_RAM_SIZE);
dinfo = drive_get(IF_PFLASH, 0, 0);
if (!dinfo && !qtest_enabled()) {
@@ -65,12 +68,10 @@ static void connex_init(MachineState *machine)
exit(1);
}
- if (!pflash_cfi01_register(0x00000000, "connext.rom", connex_rom,
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
- sector_len, 2, 0, 0, 0, 0, 0)) {
- error_report("Error registering flash memory");
- exit(1);
- }
+ /* Numonyx RC28F128J3F75 */
+ pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE,
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+ FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0);
/* Interrupt line of NIC is connected to GPIO line 36 */
smc91c111_init(&nd_table[0], 0x04000300,
@@ -81,12 +82,8 @@ static void verdex_init(MachineState *machine)
{
PXA2xxState *cpu;
DriveInfo *dinfo;
- MemoryRegion *address_space_mem = get_system_memory();
-
- uint32_t verdex_rom = 0x02000000;
- uint32_t verdex_ram = 0x10000000;
- cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type);
+ cpu = pxa270_init(VERDEX_RAM_SIZE, machine->cpu_type);
dinfo = drive_get(IF_PFLASH, 0, 0);
if (!dinfo && !qtest_enabled()) {
@@ -95,12 +92,10 @@ static void verdex_init(MachineState *machine)
exit(1);
}
- if (!pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom,
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
- sector_len, 2, 0, 0, 0, 0, 0)) {
- error_report("Error registering flash memory");
- exit(1);
- }
+ /* Micron RC28F256P30TFA */
+ pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE,
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+ FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0);
/* Interrupt line of NIC is connected to GPIO line 99 */
smc91c111_init(&nd_table[0], 0x04000300,
@@ -126,7 +121,7 @@ static void verdex_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
- mc->desc = "Gumstix Verdex (PXA270)";
+ mc->desc = "Gumstix Verdex Pro XL6P COMs (PXA270)";
mc->init = verdex_init;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index 8454b65..68329c4 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -12,6 +12,7 @@
* GNU GPL, version 2 or (at your option) any later version.
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "hw/arm/pxa.h"
@@ -99,20 +100,20 @@ static const struct keymap map[0xE0] = {
enum mainstone_model_e { mainstone };
-#define MAINSTONE_RAM 0x04000000
-#define MAINSTONE_ROM 0x00800000
-#define MAINSTONE_FLASH 0x02000000
+#define MAINSTONE_RAM_SIZE (64 * MiB)
+#define MAINSTONE_ROM_SIZE (8 * MiB)
+#define MAINSTONE_FLASH_SIZE (32 * MiB)
static struct arm_boot_info mainstone_binfo = {
.loader_start = PXA2XX_SDRAM_BASE,
- .ram_size = 0x04000000,
+ .ram_size = MAINSTONE_RAM_SIZE,
};
-static void mainstone_common_init(MemoryRegion *address_space_mem,
- MachineState *machine,
+#define FLASH_SECTOR_SIZE (256 * KiB)
+
+static void mainstone_common_init(MachineState *machine,
enum mainstone_model_e model, int arm_id)
{
- uint32_t sector_len = 256 * 1024;
hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
PXA2xxState *mpu;
DeviceState *mst_irq;
@@ -121,23 +122,19 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
MemoryRegion *rom = g_new(MemoryRegion, 1);
/* Setup CPU & memory */
- mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,
- machine->cpu_type);
- memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
+ mpu = pxa270_init(mainstone_binfo.ram_size, machine->cpu_type);
+ memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM_SIZE,
&error_fatal);
- memory_region_add_subregion(address_space_mem, 0, rom);
+ memory_region_add_subregion(get_system_memory(), 0x00000000, rom);
/* There are two 32MiB flash devices on the board */
for (i = 0; i < 2; i ++) {
dinfo = drive_get(IF_PFLASH, 0, i);
- if (!pflash_cfi01_register(mainstone_flash_base[i],
- i ? "mainstone.flash1" : "mainstone.flash0",
- MAINSTONE_FLASH,
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
- sector_len, 4, 0, 0, 0, 0, 0)) {
- error_report("Error registering flash memory");
- exit(1);
- }
+ pflash_cfi01_register(mainstone_flash_base[i],
+ i ? "mainstone.flash1" : "mainstone.flash0",
+ MAINSTONE_FLASH_SIZE,
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+ FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
}
mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
@@ -165,7 +162,7 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
static void mainstone_init(MachineState *machine)
{
- mainstone_common_init(get_system_memory(), machine, mainstone, 0x196);
+ mainstone_common_init(machine, mainstone, 0x196);
}
static void mainstone2_machine_init(MachineClass *mc)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 92f9f6e..76d4d65 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -12,6 +12,7 @@ arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
+arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index b65c020..73e2b7e 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -10,6 +10,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/sysbus.h"
@@ -1196,6 +1197,8 @@ static const TypeInfo musicpal_key_info = {
.class_init = musicpal_key_class_init,
};
+#define FLASH_SECTOR_SIZE (64 * KiB)
+
static struct arm_boot_info musicpal_binfo = {
.loader_start = 0x0,
.board_id = 0x20e,
@@ -1264,8 +1267,8 @@ static void musicpal_init(MachineState *machine)
BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
flash_size = blk_getlength(blk);
- if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
- flash_size != 32*1024*1024) {
+ if (flash_size != 8 * MiB && flash_size != 16 * MiB &&
+ flash_size != 32 * MiB) {
error_report("Invalid flash image size");
exit(1);
}
@@ -1277,7 +1280,7 @@ static void musicpal_init(MachineState *machine)
*/
pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX,
"musicpal.flash", flash_size,
- blk, 0x10000,
+ blk, FLASH_SECTOR_SIZE,
MP_FLASH_SIZE_MAX / flash_size,
2, 0x00BF, 0x236D, 0x0000, 0x0000,
0x5555, 0x2AAA, 0);
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
new file mode 100644
index 0000000..3aa61c9
--- /dev/null
+++ b/hw/arm/olimex-stm32-h405.c
@@ -0,0 +1,69 @@
+/*
+ * ST STM32VLDISCOVERY machine
+ * Olimex STM32-H405 machine
+ *
+ * Copyright (c) 2022 Felipe Balbi <balbi@kernel.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
+#include "qemu/error-report.h"
+#include "hw/arm/stm32f405_soc.h"
+#include "hw/arm/boot.h"
+
+/* olimex-stm32-h405 implementation is derived from netduinoplus2 */
+
+/* Main SYSCLK frequency in Hz (168MHz) */
+#define SYSCLK_FRQ 168000000ULL
+
+static void olimex_stm32_h405_init(MachineState *machine)
+{
+ DeviceState *dev;
+ Clock *sysclk;
+
+ /* This clock doesn't need migration because it is fixed-frequency */
+ sysclk = clock_new(OBJECT(machine), "SYSCLK");
+ clock_set_hz(sysclk, SYSCLK_FRQ);
+
+ dev = qdev_new(TYPE_STM32F405_SOC);
+ qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
+ qdev_connect_clock_in(dev, "sysclk", sysclk);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+ armv7m_load_kernel(ARM_CPU(first_cpu),
+ machine->kernel_filename,
+ 0, FLASH_SIZE);
+}
+
+static void olimex_stm32_h405_machine_init(MachineClass *mc)
+{
+ mc->desc = "Olimex STM32-H405 (Cortex-M4)";
+ mc->init = olimex_stm32_h405_init;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
+
+ /* SRAM pre-allocated as part of the SoC instantiation */
+ mc->default_ram_size = 0;
+}
+
+DEFINE_MACHINE("olimex-stm32-h405", olimex_stm32_h405_machine_init)
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
index f693faa..559c066 100644
--- a/hw/arm/omap1.c
+++ b/hw/arm/omap1.c
@@ -176,7 +176,7 @@ static void omap_timer_fire(void *opaque)
static void omap_timer_tick(void *opaque)
{
- struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
+ struct omap_mpu_timer_s *timer = opaque;
omap_timer_sync(timer);
omap_timer_fire(timer);
@@ -185,7 +185,7 @@ static void omap_timer_tick(void *opaque)
static void omap_timer_clk_update(void *opaque, int line, int on)
{
- struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
+ struct omap_mpu_timer_s *timer = opaque;
omap_timer_sync(timer);
timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
@@ -202,7 +202,7 @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
+ struct omap_mpu_timer_s *s = opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
@@ -226,7 +226,7 @@ static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
static void omap_mpu_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
+ struct omap_mpu_timer_s *s = opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);
@@ -308,7 +308,7 @@ struct omap_watchdog_timer_s {
static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
+ struct omap_watchdog_timer_s *s = opaque;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
@@ -333,7 +333,7 @@ static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
static void omap_wd_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
+ struct omap_watchdog_timer_s *s = opaque;
if (size != 2) {
omap_badwidth_write16(opaque, addr, value);
@@ -431,7 +431,7 @@ struct omap_32khz_timer_s {
static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
+ struct omap_32khz_timer_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 4) {
@@ -458,7 +458,7 @@ static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
static void omap_os_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
+ struct omap_32khz_timer_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 4) {
@@ -532,7 +532,7 @@ static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *s = opaque;
uint16_t ret;
if (size != 2) {
@@ -600,7 +600,7 @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *s = opaque;
int64_t now, ticks;
int div, mult;
static const int bypass_div[4] = { 1, 2, 4, 4 };
@@ -765,7 +765,7 @@ static void omap_ulpd_pm_init(MemoryRegion *system_memory,
static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *s = opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
@@ -876,7 +876,7 @@ static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
static void omap_pin_cfg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *s = opaque;
uint32_t diff;
if (size != 4) {
@@ -988,7 +988,7 @@ static void omap_pin_cfg_init(MemoryRegion *system_memory,
static uint64_t omap_id_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *s = opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
@@ -1070,7 +1070,7 @@ static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *s = opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
@@ -1103,7 +1103,7 @@ static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
static void omap_mpui_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *s = opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);
@@ -1168,7 +1168,7 @@ struct omap_tipb_bridge_s {
static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
+ struct omap_tipb_bridge_s *s = opaque;
if (size < 2) {
return omap_badwidth_read16(opaque, addr);
@@ -1198,7 +1198,7 @@ static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
+ struct omap_tipb_bridge_s *s = opaque;
if (size < 2) {
omap_badwidth_write16(opaque, addr, value);
@@ -1269,7 +1269,7 @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *s = opaque;
uint32_t ret;
if (size != 4) {
@@ -1307,7 +1307,7 @@ static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
static void omap_tcmi_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *s = opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);
@@ -1384,7 +1384,7 @@ struct dpll_ctl_s {
static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
+ struct dpll_ctl_s *s = opaque;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
@@ -1400,7 +1400,7 @@ static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
static void omap_dpll_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
+ struct dpll_ctl_s *s = opaque;
uint16_t diff;
static const int bypass_div[4] = { 1, 2, 4, 4 };
int div, mult;
@@ -1464,7 +1464,7 @@ static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory,
static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *s = opaque;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
@@ -1668,7 +1668,7 @@ static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
static void omap_clkm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *s = opaque;
uint16_t diff;
omap_clk clk;
static const char *clkschemename[8] = {
@@ -1756,7 +1756,7 @@ static const MemoryRegionOps omap_clkm_ops = {
static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *s = opaque;
CPUState *cpu = CPU(s->cpu);
if (size != 2) {
@@ -1801,7 +1801,7 @@ static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
static void omap_clkdsp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *s = opaque;
uint16_t diff;
if (size != 2) {
@@ -1911,7 +1911,7 @@ struct omap_mpuio_s {
static void omap_mpuio_set(void *opaque, int line, int level)
{
- struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
+ struct omap_mpuio_s *s = opaque;
uint16_t prev = s->inputs;
if (level)
@@ -1947,7 +1947,7 @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
+ struct omap_mpuio_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
@@ -2007,7 +2007,7 @@ static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
static void omap_mpuio_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
+ struct omap_mpuio_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t diff;
int ln;
@@ -2104,7 +2104,7 @@ static void omap_mpuio_reset(struct omap_mpuio_s *s)
static void omap_mpuio_onoff(void *opaque, int line, int on)
{
- struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
+ struct omap_mpuio_s *s = opaque;
s->clk = on;
if (on)
@@ -2198,10 +2198,9 @@ static void omap_uwire_transfer_start(struct omap_uwire_s *s)
}
}
-static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
- unsigned size)
+static uint64_t omap_uwire_read(void *opaque, hwaddr addr, unsigned size)
{
- struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
+ struct omap_uwire_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 2) {
@@ -2235,7 +2234,7 @@ static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
static void omap_uwire_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
+ struct omap_uwire_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 2) {
@@ -2351,10 +2350,9 @@ static void omap_pwl_update(struct omap_pwl_s *s)
}
}
-static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
- unsigned size)
+static uint64_t omap_pwl_read(void *opaque, hwaddr addr, unsigned size)
{
- struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
+ struct omap_pwl_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
@@ -2374,7 +2372,7 @@ static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
static void omap_pwl_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
+ struct omap_pwl_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
@@ -2414,7 +2412,7 @@ static void omap_pwl_reset(struct omap_pwl_s *s)
static void omap_pwl_clk_update(void *opaque, int line, int on)
{
- struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
+ struct omap_pwl_s *s = opaque;
s->clk = on;
omap_pwl_update(s);
@@ -2445,10 +2443,9 @@ struct omap_pwt_s {
omap_clk clk;
};
-static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
- unsigned size)
+static uint64_t omap_pwt_read(void *opaque, hwaddr addr, unsigned size)
{
- struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
+ struct omap_pwt_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
@@ -2470,7 +2467,7 @@ static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
static void omap_pwt_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
+ struct omap_pwt_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
@@ -2577,10 +2574,9 @@ static void omap_rtc_alarm_update(struct omap_rtc_s *s)
printf("%s: conversion failed\n", __func__);
}
-static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
- unsigned size)
+static uint64_t omap_rtc_read(void *opaque, hwaddr addr, unsigned size)
{
- struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
+ struct omap_rtc_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint8_t i;
@@ -2662,7 +2658,7 @@ static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
static void omap_rtc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
+ struct omap_rtc_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
struct tm new_tm;
time_t ti[2];
@@ -3034,7 +3030,7 @@ static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
static void omap_mcbsp_source_tick(void *opaque)
{
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+ struct omap_mcbsp_s *s = opaque;
static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
if (!s->rx_rate)
@@ -3080,7 +3076,7 @@ static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
static void omap_mcbsp_sink_tick(void *opaque)
{
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+ struct omap_mcbsp_s *s = opaque;
static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
if (!s->tx_rate)
@@ -3173,7 +3169,7 @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+ struct omap_mcbsp_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
@@ -3271,7 +3267,7 @@ static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
uint32_t value)
{
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+ struct omap_mcbsp_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
@@ -3407,7 +3403,7 @@ static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
static void omap_mcbsp_writew(void *opaque, hwaddr addr,
uint32_t value)
{
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+ struct omap_mcbsp_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (offset == 0x04) { /* DXR */
@@ -3498,7 +3494,7 @@ static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
{
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+ struct omap_mcbsp_s *s = opaque;
if (s->rx_rate) {
s->rx_req = s->codec->in.len;
@@ -3508,7 +3504,7 @@ static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
{
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+ struct omap_mcbsp_s *s = opaque;
if (s->tx_rate) {
s->tx_req = s->codec->out.size;
@@ -3590,10 +3586,9 @@ static void omap_lpg_reset(struct omap_lpg_s *s)
omap_lpg_update(s);
}
-static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
- unsigned size)
+static uint64_t omap_lpg_read(void *opaque, hwaddr addr, unsigned size)
{
- struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
+ struct omap_lpg_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
@@ -3615,7 +3610,7 @@ static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
static void omap_lpg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
+ struct omap_lpg_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
@@ -3650,7 +3645,7 @@ static const MemoryRegionOps omap_lpg_ops = {
static void omap_lpg_clk_update(void *opaque, int line, int on)
{
- struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
+ struct omap_lpg_s *s = opaque;
s->clk = on;
omap_lpg_update(s);
@@ -3713,7 +3708,7 @@ static void omap_setup_mpui_io(MemoryRegion *system_memory,
/* General chip reset */
static void omap1_mpu_reset(void *opaque)
{
- struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *mpu = opaque;
omap_dma_reset(mpu->dma);
omap_mpu_timer_reset(mpu->timer[0]);
@@ -3793,7 +3788,7 @@ static void omap_setup_dsp_mapping(MemoryRegion *system_memory,
void omap_mpu_wakeup(void *opaque, int irq, int req)
{
- struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *mpu = opaque;
CPUState *cpu = CPU(mpu->cpu);
if (cpu->halted) {
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
index 8571eed..366d6af 100644
--- a/hw/arm/omap2.c
+++ b/hw/arm/omap2.c
@@ -167,7 +167,7 @@ static inline void omap_eac_out_empty(struct omap_eac_s *s)
static void omap_eac_in_cb(void *opaque, int avail_b)
{
- struct omap_eac_s *s = (struct omap_eac_s *) opaque;
+ struct omap_eac_s *s = opaque;
s->codec.rxavail = avail_b >> 2;
omap_eac_in_refill(s);
@@ -177,7 +177,7 @@ static void omap_eac_in_cb(void *opaque, int avail_b)
static void omap_eac_out_cb(void *opaque, int free_b)
{
- struct omap_eac_s *s = (struct omap_eac_s *) opaque;
+ struct omap_eac_s *s = opaque;
s->codec.txavail = free_b >> 2;
if (s->codec.txlen)
@@ -333,10 +333,9 @@ static void omap_eac_reset(struct omap_eac_s *s)
omap_eac_interrupt_update(s);
}
-static uint64_t omap_eac_read(void *opaque, hwaddr addr,
- unsigned size)
+static uint64_t omap_eac_read(void *opaque, hwaddr addr, unsigned size)
{
- struct omap_eac_s *s = (struct omap_eac_s *) opaque;
+ struct omap_eac_s *s = opaque;
uint32_t ret;
if (size != 2) {
@@ -452,7 +451,7 @@ static uint64_t omap_eac_read(void *opaque, hwaddr addr,
static void omap_eac_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_eac_s *s = (struct omap_eac_s *) opaque;
+ struct omap_eac_s *s = opaque;
if (size != 2) {
omap_badwidth_write16(opaque, addr, value);
@@ -656,7 +655,7 @@ static void omap_sti_reset(struct omap_sti_s *s)
static uint64_t omap_sti_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_sti_s *s = (struct omap_sti_s *) opaque;
+ struct omap_sti_s *s = opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
@@ -697,7 +696,7 @@ static uint64_t omap_sti_read(void *opaque, hwaddr addr,
static void omap_sti_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_sti_s *s = (struct omap_sti_s *) opaque;
+ struct omap_sti_s *s = opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);
@@ -751,8 +750,7 @@ static const MemoryRegionOps omap_sti_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
- unsigned size)
+static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr, unsigned size)
{
OMAP_BAD_REG(addr);
return 0;
@@ -761,7 +759,7 @@ static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
static void omap_sti_fifo_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_sti_s *s = (struct omap_sti_s *) opaque;
+ struct omap_sti_s *s = opaque;
int ch = addr >> 6;
uint8_t byte = value;
@@ -1057,7 +1055,7 @@ static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
+ struct omap_prcm_s *s = opaque;
uint32_t ret;
if (size != 4) {
@@ -1369,7 +1367,7 @@ static void omap_prcm_dpll_update(struct omap_prcm_s *s)
static void omap_prcm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
+ struct omap_prcm_s *s = opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);
@@ -1849,7 +1847,7 @@ struct omap_sysctl_s {
static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
{
- struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
+ struct omap_sysctl_s *s = opaque;
int pad_offset, byte_offset;
int value;
@@ -1873,7 +1871,7 @@ static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
{
- struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
+ struct omap_sysctl_s *s = opaque;
switch (addr) {
case 0x000: /* CONTROL_REVISION */
@@ -1971,10 +1969,9 @@ static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
return 0;
}
-static void omap_sysctl_write8(void *opaque, hwaddr addr,
- uint32_t value)
+static void omap_sysctl_write8(void *opaque, hwaddr addr, uint32_t value)
{
- struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
+ struct omap_sysctl_s *s = opaque;
int pad_offset, byte_offset;
int prev_value;
@@ -1995,10 +1992,9 @@ static void omap_sysctl_write8(void *opaque, hwaddr addr,
}
}
-static void omap_sysctl_write(void *opaque, hwaddr addr,
- uint32_t value)
+static void omap_sysctl_write(void *opaque, hwaddr addr, uint32_t value)
{
- struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
+ struct omap_sysctl_s *s = opaque;
switch (addr) {
case 0x000: /* CONTROL_REVISION */
@@ -2233,7 +2229,7 @@ static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
/* General chip reset */
static void omap2_mpu_reset(void *opaque)
{
- struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *mpu = opaque;
omap_dma_reset(mpu->dma);
omap_prcm_reset(mpu->prcm);
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index 57829b3..e721292 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -26,6 +26,7 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "qapi/error.h"
#include "ui/console.h"
#include "hw/arm/omap.h"
@@ -65,7 +66,7 @@
static uint64_t static_read(void *opaque, hwaddr offset,
unsigned size)
{
- uint32_t *val = (uint32_t *) opaque;
+ uint32_t *val = opaque;
uint32_t mask = (4 / size) - 1;
return *val >> ((offset & mask) << 3);
@@ -86,17 +87,15 @@ static const MemoryRegionOps static_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-#define sdram_size 0x02000000
-#define sector_size (128 * 1024)
-#define flash0_size (16 * 1024 * 1024)
-#define flash1_size ( 8 * 1024 * 1024)
-#define flash2_size (32 * 1024 * 1024)
-#define total_ram_v1 (sdram_size + flash0_size + flash1_size + OMAP15XX_SRAM_SIZE)
-#define total_ram_v2 (sdram_size + flash2_size + OMAP15XX_SRAM_SIZE)
+#define SDRAM_SIZE (32 * MiB)
+#define SECTOR_SIZE (128 * KiB)
+#define FLASH0_SIZE (16 * MiB)
+#define FLASH1_SIZE (8 * MiB)
+#define FLASH2_SIZE (32 * MiB)
static struct arm_boot_info sx1_binfo = {
.loader_start = OMAP_EMIFF_BASE,
- .ram_size = sdram_size,
+ .ram_size = SDRAM_SIZE,
.board_id = 0x265,
};
@@ -113,7 +112,7 @@ static void sx1_init(MachineState *machine, const int version)
static uint32_t cs3val = 0x00001139;
DriveInfo *dinfo;
int fl_idx;
- uint32_t flash_size = flash0_size;
+ uint32_t flash_size = FLASH0_SIZE;
if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size);
@@ -123,7 +122,7 @@ static void sx1_init(MachineState *machine, const int version)
}
if (version == 2) {
- flash_size = flash2_size;
+ flash_size = FLASH2_SIZE;
}
memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, machine->ram);
@@ -153,13 +152,10 @@ static void sx1_init(MachineState *machine, const int version)
fl_idx = 0;
if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
- if (!pflash_cfi01_register(OMAP_CS0_BASE,
- "omap_sx1.flash0-1", flash_size,
- blk_by_legacy_dinfo(dinfo),
- sector_size, 4, 0, 0, 0, 0, 0)) {
- fprintf(stderr, "qemu: Error registering flash memory %d.\n",
- fl_idx);
- }
+ pflash_cfi01_register(OMAP_CS0_BASE,
+ "omap_sx1.flash0-1", flash_size,
+ blk_by_legacy_dinfo(dinfo),
+ SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
fl_idx++;
}
@@ -167,21 +163,18 @@ static void sx1_init(MachineState *machine, const int version)
(dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
memory_region_init_rom(flash_1, NULL, "omap_sx1.flash1-0",
- flash1_size, &error_fatal);
+ FLASH1_SIZE, &error_fatal);
memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
- "sx1.cs1", OMAP_CS1_SIZE - flash1_size);
+ "sx1.cs1", OMAP_CS1_SIZE - FLASH1_SIZE);
memory_region_add_subregion(address_space,
- OMAP_CS1_BASE + flash1_size, &cs[1]);
-
- if (!pflash_cfi01_register(OMAP_CS1_BASE,
- "omap_sx1.flash1-1", flash1_size,
- blk_by_legacy_dinfo(dinfo),
- sector_size, 4, 0, 0, 0, 0, 0)) {
- fprintf(stderr, "qemu: Error registering flash memory %d.\n",
- fl_idx);
- }
+ OMAP_CS1_BASE + FLASH1_SIZE, &cs[1]);
+
+ pflash_cfi01_register(OMAP_CS1_BASE,
+ "omap_sx1.flash1-1", FLASH1_SIZE,
+ blk_by_legacy_dinfo(dinfo),
+ SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
fl_idx++;
} else {
memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
@@ -220,7 +213,7 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
mc->init = sx1_init_v2;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
- mc->default_ram_size = sdram_size;
+ mc->default_ram_size = SDRAM_SIZE;
mc->default_ram_id = "omap1.dram";
}
@@ -238,7 +231,7 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
mc->init = sx1_init_v1;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
- mc->default_ram_size = sdram_size;
+ mc->default_ram_size = SDRAM_SIZE;
mc->default_ram_id = "omap1.dram";
}
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index 68e11dd..1457f10 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -115,7 +115,7 @@ static struct {
static void palmte_button_event(void *opaque, int keycode)
{
- struct omap_mpu_state_s *cpu = (struct omap_mpu_state_s *) opaque;
+ struct omap_mpu_state_s *cpu = opaque;
if (palmte_keymap[keycode & 0x7f].row != -1)
omap_mpuio_key(cpu->mpuio,
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 93dda83..07d5dd8 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -11,6 +11,7 @@
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qapi/error.h"
+#include "exec/address-spaces.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
@@ -2091,9 +2092,9 @@ static void pxa2xx_reset(void *opaque, int line, int level)
}
/* Initialise a PXA270 integrated chip (ARM based core). */
-PXA2xxState *pxa270_init(MemoryRegion *address_space,
- unsigned int sdram_size, const char *cpu_type)
+PXA2xxState *pxa270_init(unsigned int sdram_size, const char *cpu_type)
{
+ MemoryRegion *address_space = get_system_memory();
PXA2xxState *s;
int i;
DriveInfo *dinfo;
@@ -2230,8 +2231,9 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
}
/* Initialise a PXA255 integrated chip (ARM based core). */
-PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
+PXA2xxState *pxa255_init(unsigned int sdram_size)
{
+ MemoryRegion *address_space = get_system_memory();
PXA2xxState *s;
int i;
DriveInfo *dinfo;
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index 5aab0b8..f732fe0 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -986,18 +986,16 @@ static void spitz_common_init(MachineState *machine)
SpitzMachineState *sms = SPITZ_MACHINE(machine);
enum spitz_model_e model = smc->model;
PXA2xxState *mpu;
- MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *rom = g_new(MemoryRegion, 1);
/* Setup CPU & memory */
- mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
- machine->cpu_type);
+ mpu = pxa270_init(spitz_binfo.ram_size, machine->cpu_type);
sms->mpu = mpu;
sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
memory_region_init_rom(rom, NULL, "spitz.rom", SPITZ_ROM, &error_fatal);
- memory_region_add_subregion(address_space_mem, 0, rom);
+ memory_region_add_subregion(get_system_memory(), 0, rom);
/* Setup peripherals */
spitz_keyboard_register(mpu);
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index a9e96c3..67a2293 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -674,9 +674,8 @@ static void stellaris_i2c_init(Object *obj)
#define STELLARIS_ADC_FIFO_FULL 0x1000
#define TYPE_STELLARIS_ADC "stellaris-adc"
-typedef struct StellarisADCState stellaris_adc_state;
-DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC,
- TYPE_STELLARIS_ADC)
+typedef struct StellarisADCState StellarisADCState;
+DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC)
struct StellarisADCState {
SysBusDevice parent_obj;
@@ -700,7 +699,7 @@ struct StellarisADCState {
qemu_irq irq[4];
};
-static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
+static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n)
{
int tail;
@@ -716,7 +715,7 @@ static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
return s->fifo[n].data[tail];
}
-static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
+static void stellaris_adc_fifo_write(StellarisADCState *s, int n,
uint32_t value)
{
int head;
@@ -736,7 +735,7 @@ static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
}
-static void stellaris_adc_update(stellaris_adc_state *s)
+static void stellaris_adc_update(StellarisADCState *s)
{
int level;
int n;
@@ -749,7 +748,7 @@ static void stellaris_adc_update(stellaris_adc_state *s)
static void stellaris_adc_trigger(void *opaque, int irq, int level)
{
- stellaris_adc_state *s = (stellaris_adc_state *)opaque;
+ StellarisADCState *s = opaque;
int n;
for (n = 0; n < 4; n++) {
@@ -771,7 +770,7 @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
}
}
-static void stellaris_adc_reset(stellaris_adc_state *s)
+static void stellaris_adc_reset(StellarisADCState *s)
{
int n;
@@ -785,7 +784,7 @@ static void stellaris_adc_reset(stellaris_adc_state *s)
static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
unsigned size)
{
- stellaris_adc_state *s = (stellaris_adc_state *)opaque;
+ StellarisADCState *s = opaque;
/* TODO: Implement this. */
if (offset >= 0x40 && offset < 0xc0) {
@@ -833,7 +832,7 @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
static void stellaris_adc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
- stellaris_adc_state *s = (stellaris_adc_state *)opaque;
+ StellarisADCState *s = opaque;
/* TODO: Implement this. */
if (offset >= 0x40 && offset < 0xc0) {
@@ -901,31 +900,31 @@ static const VMStateDescription vmstate_stellaris_adc = {
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
- VMSTATE_UINT32(actss, stellaris_adc_state),
- VMSTATE_UINT32(ris, stellaris_adc_state),
- VMSTATE_UINT32(im, stellaris_adc_state),
- VMSTATE_UINT32(emux, stellaris_adc_state),
- VMSTATE_UINT32(ostat, stellaris_adc_state),
- VMSTATE_UINT32(ustat, stellaris_adc_state),
- VMSTATE_UINT32(sspri, stellaris_adc_state),
- VMSTATE_UINT32(sac, stellaris_adc_state),
- VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
- VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
- VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
- VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
- VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
- VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
- VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
- VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
- VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
- VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
- VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
- VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
- VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
- VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
- VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
- VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
- VMSTATE_UINT32(noise, stellaris_adc_state),
+ VMSTATE_UINT32(actss, StellarisADCState),
+ VMSTATE_UINT32(ris, StellarisADCState),
+ VMSTATE_UINT32(im, StellarisADCState),
+ VMSTATE_UINT32(emux, StellarisADCState),
+ VMSTATE_UINT32(ostat, StellarisADCState),
+ VMSTATE_UINT32(ustat, StellarisADCState),
+ VMSTATE_UINT32(sspri, StellarisADCState),
+ VMSTATE_UINT32(sac, StellarisADCState),
+ VMSTATE_UINT32(fifo[0].state, StellarisADCState),
+ VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16),
+ VMSTATE_UINT32(ssmux[0], StellarisADCState),
+ VMSTATE_UINT32(ssctl[0], StellarisADCState),
+ VMSTATE_UINT32(fifo[1].state, StellarisADCState),
+ VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16),
+ VMSTATE_UINT32(ssmux[1], StellarisADCState),
+ VMSTATE_UINT32(ssctl[1], StellarisADCState),
+ VMSTATE_UINT32(fifo[2].state, StellarisADCState),
+ VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16),
+ VMSTATE_UINT32(ssmux[2], StellarisADCState),
+ VMSTATE_UINT32(ssctl[2], StellarisADCState),
+ VMSTATE_UINT32(fifo[3].state, StellarisADCState),
+ VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16),
+ VMSTATE_UINT32(ssmux[3], StellarisADCState),
+ VMSTATE_UINT32(ssctl[3], StellarisADCState),
+ VMSTATE_UINT32(noise, StellarisADCState),
VMSTATE_END_OF_LIST()
}
};
@@ -933,7 +932,7 @@ static const VMStateDescription vmstate_stellaris_adc = {
static void stellaris_adc_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
- stellaris_adc_state *s = STELLARIS_ADC(obj);
+ StellarisADCState *s = STELLARIS_ADC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
int n;
@@ -1381,7 +1380,7 @@ static void stellaris_adc_class_init(ObjectClass *klass, void *data)
static const TypeInfo stellaris_adc_info = {
.name = TYPE_STELLARIS_ADC,
.parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(stellaris_adc_state),
+ .instance_size = sizeof(StellarisADCState),
.instance_init = stellaris_adc_init,
.class_init = stellaris_adc_class_init,
};
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
index c07947d..cef23d7 100644
--- a/hw/arm/stm32f405_soc.c
+++ b/hw/arm/stm32f405_soc.c
@@ -139,6 +139,14 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
}
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
+ memory_region_init_ram(&s->ccm, NULL, "STM32F405.ccm", CCM_SIZE,
+ &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(system_memory, CCM_BASE_ADDRESS, &s->ccm);
+
armv7m = DEVICE(&s->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index d5a6763..3ca2e44 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -242,7 +242,7 @@ static void tosa_init(MachineState *machine)
TC6393xbState *tmio;
DeviceState *scp0, *scp1;
- mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);
+ mpu = pxa255_init(tosa_binfo.ram_size);
memory_region_init_rom(rom, NULL, "tosa.rom", TOSA_ROM, &error_fatal);
memory_region_add_subregion(address_space_mem, 0, rom);
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index ecc1f6c..43172d7 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -385,13 +385,11 @@ static void versatile_init(MachineState *machine, int board_id)
/* 0x34000000 NOR Flash */
dinfo = drive_get(IF_PFLASH, 0, 0);
- if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash",
+ pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash",
VERSATILE_FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
VERSATILE_FLASH_SECT_SIZE,
- 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
- fprintf(stderr, "qemu: Error registering flash memory.\n");
- }
+ 4, 0x0089, 0x0018, 0x0000, 0x0, 0);
versatile_binfo.ram_size = machine->ram_size;
versatile_binfo.board_id = board_id;
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index e1d1983..7572367 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -659,10 +659,6 @@ static void vexpress_common_init(MachineState *machine)
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
dinfo);
- if (!pflash0) {
- error_report("vexpress: error registering flash 0");
- exit(1);
- }
if (map[VE_NORFLASHALIAS] != -1) {
/* Map flash 0 as an alias into low memory */
@@ -673,11 +669,7 @@ static void vexpress_common_init(MachineState *machine)
}
dinfo = drive_get(IF_PFLASH, 0, 1);
- if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
- dinfo)) {
- error_report("vexpress: error registering flash 1");
- exit(1);
- }
+ ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo);
sram_size = 0x2000000;
memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index 9c1e876..dc25304 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -12,6 +12,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "hw/arm/pxa.h"
#include "hw/arm/boot.h"
#include "hw/i2c/i2c.h"
@@ -297,10 +298,10 @@ static const TypeInfo aer915_info = {
.class_init = aer915_class_init,
};
+#define FLASH_SECTOR_SIZE (64 * KiB)
+
static void z2_init(MachineState *machine)
{
- MemoryRegion *address_space_mem = get_system_memory();
- uint32_t sector_len = 0x10000;
PXA2xxState *mpu;
DriveInfo *dinfo;
void *z2_lcd;
@@ -308,15 +309,12 @@ static void z2_init(MachineState *machine)
DeviceState *wm;
/* Setup CPU & memory */
- mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type);
+ mpu = pxa270_init(z2_binfo.ram_size, machine->cpu_type);
dinfo = drive_get(IF_PFLASH, 0, 0);
- if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
- sector_len, 4, 0, 0, 0, 0, 0)) {
- error_report("Error registering flash memory");
- exit(1);
- }
+ pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+ FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
/* setup keypad */
pxa27x_register_keypad(mpu->kp, map, 0x100);
generated by cgit v1.1 at 2025-04-14 19:54:47 +0000