diff options
50 files changed, 358 insertions, 256 deletions
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 6df3a4d..439a4ef 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -2188,9 +2188,9 @@ void kvm_flush_coalesced_mmio_buffer(void) ent = &ring->coalesced_mmio[ring->first]; if (ent->pio == 1) { - address_space_rw(&address_space_io, ent->phys_addr, - MEMTXATTRS_UNSPECIFIED, ent->data, - ent->len, true); + address_space_write(&address_space_io, ent->phys_addr, + MEMTXATTRS_UNSPECIFIED, ent->data, + ent->len); } else { cpu_physical_memory_write(ent->phys_addr, ent->data, ent->len); } diff --git a/dma-helpers.c b/dma-helpers.c index d3871dc..e8a26e8 100644 --- a/dma-helpers.c +++ b/dma-helpers.c @@ -28,8 +28,8 @@ int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len) memset(fillbuf, c, FILLBUF_SIZE); while (len > 0) { l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE; - error |= address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, - fillbuf, l, true); + error |= address_space_write(as, addr, MEMTXATTRS_UNSPECIFIED, + fillbuf, l); len -= l; addr += l; } @@ -2736,9 +2736,9 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, } static MemTxResult flatview_read(FlatView *fv, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, hwaddr len); + MemTxAttrs attrs, void *buf, hwaddr len); static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, hwaddr len); + const void *buf, hwaddr len); static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len, bool is_write, MemTxAttrs attrs); @@ -2975,11 +2975,12 @@ MemoryRegion *get_system_io(void) /* physical memory access (slow version, mainly for debug) */ #if defined(CONFIG_USER_ONLY) int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, - uint8_t *buf, target_ulong len, int is_write) + void *ptr, target_ulong len, bool is_write) { int flags; target_ulong l, page; void * p; + uint8_t *buf = ptr; while (len > 0) { page = addr & TARGET_PAGE_MASK; @@ -3103,14 +3104,15 @@ static bool prepare_mmio_access(MemoryRegion *mr) /* Called within RCU critical section. */ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, + const void *ptr, hwaddr len, hwaddr addr1, hwaddr l, MemoryRegion *mr) { - uint8_t *ptr; + uint8_t *ram_ptr; uint64_t val; MemTxResult result = MEMTX_OK; bool release_lock = false; + const uint8_t *buf = ptr; for (;;) { if (!memory_access_is_direct(mr, true)) { @@ -3123,8 +3125,8 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, size_memop(l), attrs); } else { /* RAM case */ - ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); - memcpy(ptr, buf, l); + ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); + memcpy(ram_ptr, buf, l); invalidate_and_set_dirty(mr, addr1, l); } @@ -3150,7 +3152,7 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, /* Called from RCU critical section. */ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, hwaddr len) + const void *buf, hwaddr len) { hwaddr l; hwaddr addr1; @@ -3167,14 +3169,15 @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, /* Called within RCU critical section. */ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, + MemTxAttrs attrs, void *ptr, hwaddr len, hwaddr addr1, hwaddr l, MemoryRegion *mr) { - uint8_t *ptr; + uint8_t *ram_ptr; uint64_t val; MemTxResult result = MEMTX_OK; bool release_lock = false; + uint8_t *buf = ptr; for (;;) { if (!memory_access_is_direct(mr, false)) { @@ -3186,8 +3189,8 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, stn_he_p(buf, l, val); } else { /* RAM case */ - ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); - memcpy(buf, ptr, l); + ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); + memcpy(buf, ram_ptr, l); } if (release_lock) { @@ -3212,7 +3215,7 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, /* Called from RCU critical section. */ static MemTxResult flatview_read(FlatView *fv, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, hwaddr len) + MemTxAttrs attrs, void *buf, hwaddr len) { hwaddr l; hwaddr addr1; @@ -3225,7 +3228,7 @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr, } MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, hwaddr len) + MemTxAttrs attrs, void *buf, hwaddr len) { MemTxResult result = MEMTX_OK; FlatView *fv; @@ -3241,7 +3244,7 @@ MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr, MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, hwaddr len) + const void *buf, hwaddr len) { MemTxResult result = MEMTX_OK; FlatView *fv; @@ -3256,7 +3259,7 @@ MemTxResult address_space_write(AddressSpace *as, hwaddr addr, } MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, - uint8_t *buf, hwaddr len, bool is_write) + void *buf, hwaddr len, bool is_write) { if (is_write) { return address_space_write(as, addr, attrs, buf, len); @@ -3265,8 +3268,8 @@ MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, } } -void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, - hwaddr len, int is_write) +void cpu_physical_memory_rw(hwaddr addr, void *buf, + hwaddr len, bool is_write) { address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED, buf, len, is_write); @@ -3280,14 +3283,15 @@ enum write_rom_type { static inline MemTxResult address_space_write_rom_internal(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, + const void *ptr, hwaddr len, enum write_rom_type type) { hwaddr l; - uint8_t *ptr; + uint8_t *ram_ptr; hwaddr addr1; MemoryRegion *mr; + const uint8_t *buf = ptr; RCU_READ_LOCK_GUARD(); while (len > 0) { @@ -3299,14 +3303,14 @@ static inline MemTxResult address_space_write_rom_internal(AddressSpace *as, l = memory_access_size(mr, l, addr1); } else { /* ROM/RAM case */ - ptr = qemu_map_ram_ptr(mr->ram_block, addr1); + ram_ptr = qemu_map_ram_ptr(mr->ram_block, addr1); switch (type) { case WRITE_DATA: - memcpy(ptr, buf, l); + memcpy(ram_ptr, buf, l); invalidate_and_set_dirty(mr, addr1, l); break; case FLUSH_CACHE: - flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l); + flush_icache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr + l); break; } } @@ -3320,7 +3324,7 @@ static inline MemTxResult address_space_write_rom_internal(AddressSpace *as, /* used for ROM loading : can write in RAM and ROM */ MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, hwaddr len) + const void *buf, hwaddr len) { return address_space_write_rom_internal(as, addr, attrs, buf, len, WRITE_DATA); @@ -3550,11 +3554,11 @@ void *address_space_map(AddressSpace *as, } /* Unmaps a memory region previously mapped by address_space_map(). - * Will also mark the memory as dirty if is_write == 1. access_len gives + * Will also mark the memory as dirty if is_write is true. access_len gives * the amount of memory that was actually read or written by the caller. */ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, - int is_write, hwaddr access_len) + bool is_write, hwaddr access_len) { if (buffer != bounce.buffer) { MemoryRegion *mr; @@ -3584,14 +3588,14 @@ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, void *cpu_physical_memory_map(hwaddr addr, hwaddr *plen, - int is_write) + bool is_write) { return address_space_map(&address_space_memory, addr, plen, is_write, MEMTXATTRS_UNSPECIFIED); } void cpu_physical_memory_unmap(void *buffer, hwaddr len, - int is_write, hwaddr access_len) + bool is_write, hwaddr access_len) { return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len); } @@ -3742,10 +3746,11 @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr, /* virtual memory access for debug (includes writing to ROM) */ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, - uint8_t *buf, target_ulong len, int is_write) + void *ptr, target_ulong len, bool is_write) { hwaddr phys_addr; target_ulong l, page; + uint8_t *buf = ptr; cpu_synchronize_state(cpu); while (len > 0) { @@ -3766,8 +3771,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr, attrs, buf, l); } else { - address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, - attrs, buf, l, 0); + address_space_read(cpu->cpu_ases[asidx].as, phys_addr, attrs, buf, + l); } len -= l; buf += l; diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 0c213ca..fef4072 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -327,8 +327,7 @@ static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) cmdline_size = strlen(info->kernel_cmdline); address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, - (const uint8_t *)info->kernel_cmdline, - cmdline_size + 1); + info->kernel_cmdline, cmdline_size + 1); cmdline_size = (cmdline_size >> 2) + 1; WRITE_WORD(p, cmdline_size + 2); WRITE_WORD(p, 0x54410009); @@ -420,8 +419,7 @@ static void set_kernel_args_old(const struct arm_boot_info *info, } s = info->kernel_cmdline; if (s) { - address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, - (const uint8_t *)s, strlen(s) + 1); + address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1); } else { WRITE_WORD(p, 0); } diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 23eb117..0f2573f 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -74,8 +74,7 @@ static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte, dma_addr_t addr = baseaddr + index * sizeof(*pte); /* TODO: guarantee 64-bit single-copy atomicity */ - ret = dma_memory_read(&address_space_memory, addr, - (uint8_t *)pte, sizeof(*pte)); + ret = dma_memory_read(&address_space_memory, addr, pte, sizeof(*pte)); if (ret != MEMTX_OK) { info->type = SMMU_PTW_ERR_WALK_EABT; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 8b5f157..57a79df 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -279,8 +279,7 @@ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, trace_smmuv3_get_ste(addr); /* TODO: guarantee 64-bit single-copy atomicity */ - ret = dma_memory_read(&address_space_memory, addr, - (void *)buf, sizeof(*buf)); + ret = dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf)); if (ret != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "Cannot fetch pte at address=0x%"PRIx64"\n", addr); @@ -301,8 +300,7 @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid, trace_smmuv3_get_cd(addr); /* TODO: guarantee 64-bit single-copy atomicity */ - ret = dma_memory_read(&address_space_memory, addr, - (void *)buf, sizeof(*buf)); + ret = dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf)); if (ret != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "Cannot fetch pte at address=0x%"PRIx64"\n", addr); @@ -406,8 +404,8 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, l2_ste_offset = sid & ((1 << s->sid_split) - 1); l1ptr = (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std)); /* TODO: guarantee 64-bit single-copy atomicity */ - ret = dma_memory_read(&address_space_memory, l1ptr, - (uint8_t *)&l1std, sizeof(l1std)); + ret = dma_memory_read(&address_space_memory, l1ptr, &l1std, + sizeof(l1std)); if (ret != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "Could not read L1PTR at 0X%"PRIx64"\n", l1ptr); diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c index c1071ec..ec67766 100644 --- a/hw/display/exynos4210_fimd.c +++ b/hw/display/exynos4210_fimd.c @@ -1164,7 +1164,8 @@ static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win) goto error_return; } - w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len, 0); + w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len, + false); if (!w->host_fb_addr) { DPRINT_ERROR("Failed to map window %u framebuffer\n", win); goto error_return; diff --git a/hw/display/milkymist-tmu2.c b/hw/display/milkymist-tmu2.c index 199f122..513c0d5 100644 --- a/hw/display/milkymist-tmu2.c +++ b/hw/display/milkymist-tmu2.c @@ -218,7 +218,7 @@ static void tmu2_start(MilkymistTMU2State *s) glGenTextures(1, &texture); glBindTexture(GL_TEXTURE_2D, texture); fb_len = 2ULL * s->regs[R_TEXHRES] * s->regs[R_TEXVRES]; - fb = cpu_physical_memory_map(s->regs[R_TEXFBUF], &fb_len, 0); + fb = cpu_physical_memory_map(s->regs[R_TEXFBUF], &fb_len, false); if (fb == NULL) { glDeleteTextures(1, &texture); glXMakeContextCurrent(s->dpy, None, None, NULL); @@ -262,7 +262,7 @@ static void tmu2_start(MilkymistTMU2State *s) /* Read the QEMU dest. framebuffer into the OpenGL framebuffer */ fb_len = 2ULL * s->regs[R_DSTHRES] * s->regs[R_DSTVRES]; - fb = cpu_physical_memory_map(s->regs[R_DSTFBUF], &fb_len, 0); + fb = cpu_physical_memory_map(s->regs[R_DSTFBUF], &fb_len, false); if (fb == NULL) { glDeleteTextures(1, &texture); glXMakeContextCurrent(s->dpy, None, None, NULL); @@ -281,7 +281,7 @@ static void tmu2_start(MilkymistTMU2State *s) /* Map the texture */ mesh_len = MESH_MAXSIZE*MESH_MAXSIZE*sizeof(struct vertex); - mesh = cpu_physical_memory_map(s->regs[R_VERTICESADDR], &mesh_len, 0); + mesh = cpu_physical_memory_map(s->regs[R_VERTICESADDR], &mesh_len, false); if (mesh == NULL) { glDeleteTextures(1, &texture); glXMakeContextCurrent(s->dpy, None, None, NULL); @@ -298,7 +298,7 @@ static void tmu2_start(MilkymistTMU2State *s) /* Write back the OpenGL framebuffer to the QEMU framebuffer */ fb_len = 2ULL * s->regs[R_DSTHRES] * s->regs[R_DSTVRES]; - fb = cpu_physical_memory_map(s->regs[R_DSTFBUF], &fb_len, 1); + fb = cpu_physical_memory_map(s->regs[R_DSTFBUF], &fb_len, true); if (fb == NULL) { glDeleteTextures(1, &texture); glXMakeContextCurrent(s->dpy, None, None, NULL); diff --git a/hw/display/omap_dss.c b/hw/display/omap_dss.c index 637aae8..32dc0d6 100644 --- a/hw/display/omap_dss.c +++ b/hw/display/omap_dss.c @@ -632,7 +632,7 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s) len = s->rfbi.pixels * 2; data_addr = s->dispc.l[0].addr[0]; - data = cpu_physical_memory_map(data_addr, &len, 0); + data = cpu_physical_memory_map(data_addr, &len, false); if (data && len != s->rfbi.pixels * 2) { cpu_physical_memory_unmap(data, len, 0, 0); data = NULL; diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c index 6ad13f2..fa4a381 100644 --- a/hw/display/omap_lcdc.c +++ b/hw/display/omap_lcdc.c @@ -91,9 +91,9 @@ static void omap_update_display(void *opaque) frame_offset = 0; if (omap_lcd->plm != 2) { - cpu_physical_memory_read(omap_lcd->dma->phys_framebuffer[ - omap_lcd->dma->current_frame], - (void *)omap_lcd->palette, 0x200); + cpu_physical_memory_read( + omap_lcd->dma->phys_framebuffer[omap_lcd->dma->current_frame], + omap_lcd->palette, 0x200); switch (omap_lcd->palette[0] >> 12 & 7) { case 3 ... 7: frame_offset += 0x200; @@ -244,8 +244,8 @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) { if (s->plm != 2 && !s->palette_done) { cpu_physical_memory_read( - s->dma->phys_framebuffer[s->dma->current_frame], - (void *)s->palette, 0x200); + s->dma->phys_framebuffer[s->dma->current_frame], + s->palette, 0x200); s->palette_done = 1; omap_lcd_interrupts(s); } diff --git a/hw/display/ramfb.c b/hw/display/ramfb.c index cd94940..7ba07c8 100644 --- a/hw/display/ramfb.c +++ b/hw/display/ramfb.c @@ -57,7 +57,7 @@ static DisplaySurface *ramfb_create_display_surface(int width, int height, } size = (hwaddr)linesize * height; - data = cpu_physical_memory_map(addr, &size, 0); + data = cpu_physical_memory_map(addr, &size, false); if (size != (hwaddr)linesize * height) { cpu_physical_memory_unmap(data, size, 0, 0); return NULL; diff --git a/hw/dma/etraxfs_dma.c b/hw/dma/etraxfs_dma.c index 47e1c6d..c4334e8 100644 --- a/hw/dma/etraxfs_dma.c +++ b/hw/dma/etraxfs_dma.c @@ -225,9 +225,8 @@ static void channel_load_g(struct fs_dma_ctrl *ctrl, int c) hwaddr addr = channel_reg(ctrl, c, RW_GROUP); /* Load and decode. FIXME: handle endianness. */ - cpu_physical_memory_read (addr, - (void *) &ctrl->channels[c].current_g, - sizeof ctrl->channels[c].current_g); + cpu_physical_memory_read(addr, &ctrl->channels[c].current_g, + sizeof(ctrl->channels[c].current_g)); } static void dump_c(int ch, struct dma_descr_context *c) @@ -257,9 +256,8 @@ static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN); /* Load and decode. FIXME: handle endianness. */ - cpu_physical_memory_read (addr, - (void *) &ctrl->channels[c].current_c, - sizeof ctrl->channels[c].current_c); + cpu_physical_memory_read(addr, &ctrl->channels[c].current_c, + sizeof(ctrl->channels[c].current_c)); D(dump_c(c, &ctrl->channels[c].current_c)); /* I guess this should update the current pos. */ @@ -275,9 +273,8 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) /* Load and decode. FIXME: handle endianness. */ D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); - cpu_physical_memory_read (addr, - (void *) &ctrl->channels[c].current_d, - sizeof ctrl->channels[c].current_d); + cpu_physical_memory_read(addr, &ctrl->channels[c].current_d, + sizeof(ctrl->channels[c].current_d)); D(dump_d(c, &ctrl->channels[c].current_d)); ctrl->channels[c].regs[RW_DATA] = addr; @@ -290,9 +287,8 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) /* Encode and store. FIXME: handle endianness. */ D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); D(dump_d(c, &ctrl->channels[c].current_d)); - cpu_physical_memory_write (addr, - (void *) &ctrl->channels[c].current_c, - sizeof ctrl->channels[c].current_c); + cpu_physical_memory_write(addr, &ctrl->channels[c].current_c, + sizeof(ctrl->channels[c].current_c)); } static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) @@ -301,9 +297,8 @@ static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) /* Encode and store. FIXME: handle endianness. */ D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); - cpu_physical_memory_write (addr, - (void *) &ctrl->channels[c].current_d, - sizeof ctrl->channels[c].current_d); + cpu_physical_memory_write(addr, &ctrl->channels[c].current_d, + sizeof(ctrl->channels[c].current_d)); } static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c) diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c index c4cf823..21e2c36 100644 --- a/hw/dma/rc4030.c +++ b/hw/dma/rc4030.c @@ -513,8 +513,8 @@ static IOMMUTLBEntry rc4030_dma_translate(IOMMUMemoryRegion *iommu, hwaddr addr, if (i < s->dma_tl_limit / sizeof(entry)) { entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry); if (address_space_read(ret.target_as, entry_address, - MEMTXATTRS_UNSPECIFIED, (unsigned char *)&entry, - sizeof(entry)) == MEMTX_OK) { + MEMTXATTRS_UNSPECIFIED, &entry, sizeof(entry)) + == MEMTX_OK) { ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1); ret.perm = IOMMU_RW; } @@ -590,7 +590,7 @@ static const VMStateDescription vmstate_rc4030 = { }; static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, - int len, int is_write) + int len, bool is_write) { rc4030State *s = opaque; hwaddr dma_addr; @@ -630,13 +630,13 @@ struct rc4030DMAState { void rc4030_dma_read(void *dma, uint8_t *buf, int len) { rc4030_dma s = dma; - rc4030_do_dma(s->opaque, s->n, buf, len, 0); + rc4030_do_dma(s->opaque, s->n, buf, len, false); } void rc4030_dma_write(void *dma, uint8_t *buf, int len) { rc4030_dma s = dma; - rc4030_do_dma(s->opaque, s->n, buf, len, 1); + rc4030_do_dma(s->opaque, s->n, buf, len, true); } static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n) diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c index 8fb83f5..1c1b142 100644 --- a/hw/dma/xlnx-zdma.c +++ b/hw/dma/xlnx-zdma.c @@ -311,8 +311,7 @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf) return false; } - address_space_rw(s->dma_as, addr, s->attr, - buf, sizeof(XlnxZDMADescr), false); + address_space_read(s->dma_as, addr, s->attr, buf, sizeof(XlnxZDMADescr)); return true; } @@ -364,7 +363,7 @@ static uint64_t zdma_update_descr_addr(XlnxZDMA *s, bool type, } else { addr = zdma_get_regaddr64(s, basereg); addr += sizeof(s->dsc_dst); - address_space_rw(s->dma_as, addr, s->attr, (void *) &next, 8, false); + address_space_read(s->dma_as, addr, s->attr, &next, 8); zdma_put_regaddr64(s, basereg, next); } return next; @@ -416,8 +415,7 @@ static void zdma_write_dst(XlnxZDMA *s, uint8_t *buf, uint32_t len) } } - address_space_rw(s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen, - true); + address_space_write(s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen); if (burst_type == AXI_BURST_INCR) { s->dsc_dst.addr += dlen; } @@ -493,8 +491,7 @@ static void zdma_process_descr(XlnxZDMA *s) len = s->cfg.bus_width / 8; } } else { - address_space_rw(s->dma_as, src_addr, s->attr, s->buf, len, - false); + address_space_read(s->dma_as, src_addr, s->attr, s->buf, len); if (burst_type == AXI_BURST_INCR) { src_addr += len; } diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 68264a2..13d91e1 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1461,7 +1461,7 @@ static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes) ad->cur_cmd->status = cpu_to_le32(tx_bytes); } -static int ahci_dma_rw_buf(IDEDMA *dma, int is_write) +static int ahci_dma_rw_buf(IDEDMA *dma, bool is_write) { AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); IDEState *s = &ad->port.ifs[0]; diff --git a/hw/ide/core.c b/hw/ide/core.c index 80000eb..689bb36 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -2570,7 +2570,7 @@ static void ide_init1(IDEBus *bus, int unit) ide_sector_write_timer_cb, s); } -static int ide_nop_int(IDEDMA *dma, int x) +static int ide_nop_int(IDEDMA *dma, bool is_write) { return 0; } diff --git a/hw/ide/macio.c b/hw/ide/macio.c index 7a8470e..a9f25e5 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -376,7 +376,7 @@ static void macio_ide_reset(DeviceState *dev) ide_bus_reset(&d->bus); } -static int ide_nop_int(IDEDMA *dma, int x) +static int ide_nop_int(IDEDMA *dma, bool is_write) { return 0; } diff --git a/hw/ide/pci.c b/hw/ide/pci.c index cce1da8..1a6a287 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -181,7 +181,7 @@ static int32_t bmdma_prepare_buf(IDEDMA *dma, int32_t limit) } /* return 0 if buffer completed */ -static int bmdma_rw_buf(IDEDMA *dma, int is_write) +static int bmdma_rw_buf(IDEDMA *dma, bool is_write) { BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); IDEState *s = bmdma_active_if(bm); diff --git a/hw/misc/pc-testdev.c b/hw/misc/pc-testdev.c index 0fb84dd..8aa8e65 100644 --- a/hw/misc/pc-testdev.c +++ b/hw/misc/pc-testdev.c @@ -125,7 +125,7 @@ static void test_flush_page_write(void *opaque, hwaddr addr, uint64_t data, unsigned len) { hwaddr page = 4096; - void *a = cpu_physical_memory_map(data & ~0xffful, &page, 0); + void *a = cpu_physical_memory_map(data & ~0xffful, &page, false); /* We might not be able to get the full page, only mprotect what we actually have mapped */ diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 871fcf2..ddabdb3 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -871,7 +871,7 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) /* read current descriptor */ address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *)s->rx_desc[q], + s->rx_desc[q], sizeof(uint32_t) * gem_get_desc_len(s, true)); /* Descriptor owned by software ? */ @@ -1029,9 +1029,8 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) /* Descriptor write-back. */ desc_addr = gem_get_rx_desc_addr(s, q); - address_space_write(&s->dma_as, desc_addr, - MEMTXATTRS_UNSPECIFIED, - (uint8_t *)s->rx_desc[q], + address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, + s->rx_desc[q], sizeof(uint32_t) * gem_get_desc_len(s, true)); /* Next descriptor */ @@ -1137,7 +1136,7 @@ static void gem_transmit(CadenceGEMState *s) DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); address_space_read(&s->dma_as, packet_desc_addr, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, + MEMTXATTRS_UNSPECIFIED, desc, sizeof(uint32_t) * gem_get_desc_len(s, false)); /* Handle all descriptors owned by hardware */ while (tx_desc_get_used(desc) == 0) { @@ -1185,14 +1184,12 @@ static void gem_transmit(CadenceGEMState *s) * the processor. */ address_space_read(&s->dma_as, desc_addr, - MEMTXATTRS_UNSPECIFIED, - (uint8_t *)desc_first, + MEMTXATTRS_UNSPECIFIED, desc_first, sizeof(desc_first)); tx_desc_set_used(desc_first); address_space_write(&s->dma_as, desc_addr, - MEMTXATTRS_UNSPECIFIED, - (uint8_t *)desc_first, - sizeof(desc_first)); + MEMTXATTRS_UNSPECIFIED, desc_first, + sizeof(desc_first)); /* Advance the hardware current descriptor past this packet */ if (tx_desc_get_wrap(desc)) { s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; @@ -1246,8 +1243,8 @@ static void gem_transmit(CadenceGEMState *s) } DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); address_space_read(&s->dma_as, packet_desc_addr, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, - sizeof(uint32_t) * gem_get_desc_len(s, false)); + MEMTXATTRS_UNSPECIFIED, desc, + sizeof(uint32_t) * gem_get_desc_len(s, false)); } if (tx_desc_get_used(desc)) { diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index a134d43..7045193 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -275,8 +275,8 @@ static void dp8393x_do_load_cam(dp8393xState *s) while (s->regs[SONIC_CDC] & 0x1f) { /* Fill current entry */ - address_space_rw(&s->as, dp8393x_cdp(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + address_space_read(&s->as, dp8393x_cdp(s), + MEMTXATTRS_UNSPECIFIED, s->data, size); s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff; s->cam[index][1] = dp8393x_get(s, width, 1) >> 8; s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff; @@ -293,8 +293,8 @@ static void dp8393x_do_load_cam(dp8393xState *s) } /* Read CAM enable */ - address_space_rw(&s->as, dp8393x_cdp(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + address_space_read(&s->as, dp8393x_cdp(s), + MEMTXATTRS_UNSPECIFIED, s->data, size); s->regs[SONIC_CE] = dp8393x_get(s, width, 0); DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); @@ -311,8 +311,8 @@ static void dp8393x_do_read_rra(dp8393xState *s) /* Read memory */ width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; size = sizeof(uint16_t) * 4 * width; - address_space_rw(&s->as, dp8393x_rrp(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + address_space_read(&s->as, dp8393x_rrp(s), + MEMTXATTRS_UNSPECIFIED, s->data, size); /* Update SONIC registers */ s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0); @@ -426,8 +426,8 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) size = sizeof(uint16_t) * 6 * width; s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); - address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, + MEMTXATTRS_UNSPECIFIED, s->data, size); tx_len = 0; /* Update registers */ @@ -451,17 +451,19 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) if (tx_len + len > sizeof(s->tx_buffer)) { len = sizeof(s->tx_buffer) - tx_len; } - address_space_rw(&s->as, dp8393x_tsa(s), - MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0); + address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED, + &s->tx_buffer[tx_len], len); tx_len += len; i++; if (i != s->regs[SONIC_TFC]) { /* Read next fragment details */ size = sizeof(uint16_t) * 3 * width; - address_space_rw(&s->as, - dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + address_space_read(&s->as, + dp8393x_ttda(s) + + sizeof(uint16_t) * width * (4 + 3 * i), + MEMTXATTRS_UNSPECIFIED, s->data, + size); s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0); s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1); s->regs[SONIC_TFS] = dp8393x_get(s, width, 2); @@ -494,18 +496,18 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) dp8393x_put(s, width, 0, s->regs[SONIC_TCR] & 0x0fff); /* status */ size = sizeof(uint16_t) * width; - address_space_rw(&s->as, - dp8393x_ttda(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1); + address_space_write(&s->as, dp8393x_ttda(s), + MEMTXATTRS_UNSPECIFIED, s->data, size); if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { /* Read footer of packet */ size = sizeof(uint16_t) * width; - address_space_rw(&s->as, - dp8393x_ttda(s) + - sizeof(uint16_t) * - (4 + 3 * s->regs[SONIC_TFC]) * width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + address_space_read(&s->as, + dp8393x_ttda(s) + + sizeof(uint16_t) * width + * (4 + 3 * s->regs[SONIC_TFC]), + MEMTXATTRS_UNSPECIFIED, s->data, + size); s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1; if (dp8393x_get(s, width, 0) & 0x1) { /* EOL detected */ @@ -767,8 +769,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, /* Are we still in resource exhaustion? */ size = sizeof(uint16_t) * 1 * width; address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; - address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, - (uint8_t *)s->data, size, 0); + address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED, + s->data, size); if (dp8393x_get(s, width, 0) & 0x1) { /* Still EOL ; stop reception */ return -1; @@ -787,11 +789,11 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, /* Put packet into RBA */ DPRINTF("Receive packet at %08x\n", dp8393x_crba(s)); address = dp8393x_crba(s); - address_space_rw(&s->as, address, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len, 1); + address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, + buf, rx_len); address += rx_len; - address_space_rw(&s->as, address, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1); + address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, + &checksum, 4); rx_len += 4; s->regs[SONIC_CRBA1] = address >> 16; s->regs[SONIC_CRBA0] = address & 0xffff; @@ -819,13 +821,15 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ size = sizeof(uint16_t) * 5 * width; - address_space_rw(&s->as, dp8393x_crda(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1); + address_space_write(&s->as, dp8393x_crda(s), + MEMTXATTRS_UNSPECIFIED, + s->data, size); /* Move to next descriptor */ size = sizeof(uint16_t) * width; - address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + address_space_read(&s->as, + dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, + MEMTXATTRS_UNSPECIFIED, s->data, size); s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); if (s->regs[SONIC_LLFA] & 0x1) { /* EOL detected */ @@ -838,8 +842,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, offset += sizeof(uint16_t); } s->data[0] = 0; - address_space_rw(&s->as, offset, MEMTXATTRS_UNSPECIFIED, - (uint8_t *)s->data, sizeof(uint16_t), 1); + address_space_write(&s->as, offset, MEMTXATTRS_UNSPECIFIED, + s->data, sizeof(uint16_t)); s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff); diff --git a/hw/net/i82596.c b/hw/net/i82596.c index 3a0e1ec..fe9f239 100644 --- a/hw/net/i82596.c +++ b/hw/net/i82596.c @@ -148,8 +148,8 @@ static void i82596_transmit(I82596State *s, uint32_t addr) if (s->nic && len) { assert(len <= sizeof(s->tx_buffer)); - address_space_rw(&address_space_memory, tba, - MEMTXATTRS_UNSPECIFIED, s->tx_buffer, len, 0); + address_space_read(&address_space_memory, tba, + MEMTXATTRS_UNSPECIFIED, s->tx_buffer, len); DBG(PRINT_PKTHDR("Send", &s->tx_buffer)); DBG(printf("Sending %d bytes\n", len)); qemu_send_packet(qemu_get_queue(s->nic), s->tx_buffer, len); @@ -172,8 +172,8 @@ static void set_individual_address(I82596State *s, uint32_t addr) nc = qemu_get_queue(s->nic); m = s->conf.macaddr.a; - address_space_rw(&address_space_memory, addr + 8, - MEMTXATTRS_UNSPECIFIED, m, ETH_ALEN, 0); + address_space_read(&address_space_memory, addr + 8, + MEMTXATTRS_UNSPECIFIED, m, ETH_ALEN); qemu_format_nic_info_str(nc, m); trace_i82596_new_mac(nc->info_str); } @@ -190,9 +190,8 @@ static void set_multicast_list(I82596State *s, uint32_t addr) } for (i = 0; i < mc_count; i++) { uint8_t multicast_addr[ETH_ALEN]; - address_space_rw(&address_space_memory, - addr + i * ETH_ALEN, MEMTXATTRS_UNSPECIFIED, - multicast_addr, ETH_ALEN, 0); + address_space_read(&address_space_memory, addr + i * ETH_ALEN, + MEMTXATTRS_UNSPECIFIED, multicast_addr, ETH_ALEN); DBG(printf("Add multicast entry " MAC_FMT "\n", MAC_ARG(multicast_addr))); unsigned mcast_idx = (net_crc32(multicast_addr, ETH_ALEN) & @@ -260,8 +259,8 @@ static void command_loop(I82596State *s) byte_cnt = MAX(byte_cnt, 4); byte_cnt = MIN(byte_cnt, sizeof(s->config)); /* copy byte_cnt max. */ - address_space_rw(&address_space_memory, s->cmd_p + 8, - MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt, 0); + address_space_read(&address_space_memory, s->cmd_p + 8, + MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt); /* config byte according to page 35ff */ s->config[2] &= 0x82; /* mask valid bits */ s->config[2] |= 0x40; @@ -640,14 +639,14 @@ ssize_t i82596_receive(NetClientState *nc, const uint8_t *buf, size_t sz) } rba = get_uint32(rbd + 8); /* printf("rba is 0x%x\n", rba); */ - address_space_rw(&address_space_memory, rba, - MEMTXATTRS_UNSPECIFIED, (void *)buf, num, 1); + address_space_write(&address_space_memory, rba, + MEMTXATTRS_UNSPECIFIED, buf, num); rba += num; buf += num; len -= num; if (len == 0) { /* copy crc */ - address_space_rw(&address_space_memory, rba - 4, - MEMTXATTRS_UNSPECIFIED, crc_ptr, 4, 1); + address_space_write(&address_space_memory, rba - 4, + MEMTXATTRS_UNSPECIFIED, crc_ptr, 4); } num |= 0x4000; /* set F BIT */ diff --git a/hw/net/lasi_i82596.c b/hw/net/lasi_i82596.c index 427b3fb..52637a5 100644 --- a/hw/net/lasi_i82596.c +++ b/hw/net/lasi_i82596.c @@ -55,8 +55,9 @@ static void lasi_82596_mem_write(void *opaque, hwaddr addr, * Provided for SeaBIOS only. Write MAC of Network card to addr @val. * Needed for the PDC_LAN_STATION_ID_READ PDC call. */ - address_space_rw(&address_space_memory, val, - MEMTXATTRS_UNSPECIFIED, d->state.conf.macaddr.a, ETH_ALEN, 1); + address_space_write(&address_space_memory, val, + MEMTXATTRS_UNSPECIFIED, d->state.conf.macaddr.a, + ETH_ALEN); break; } } diff --git a/hw/nvram/spapr_nvram.c b/hw/nvram/spapr_nvram.c index 877ddef..15d0828 100644 --- a/hw/nvram/spapr_nvram.c +++ b/hw/nvram/spapr_nvram.c @@ -89,7 +89,7 @@ static void rtas_nvram_fetch(PowerPCCPU *cpu, SpaprMachineState *spapr, assert(nvram->buf); - membuf = cpu_physical_memory_map(buffer, &len, 1); + membuf = cpu_physical_memory_map(buffer, &len, true); memcpy(membuf, nvram->buf + offset, len); cpu_physical_memory_unmap(membuf, len, 1, len); @@ -127,7 +127,7 @@ static void rtas_nvram_store(PowerPCCPU *cpu, SpaprMachineState *spapr, return; } - membuf = cpu_physical_memory_map(buffer, &len, 0); + membuf = cpu_physical_memory_map(buffer, &len, false); alen = len; if (nvram->blk) { diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 5989d72..f150dec 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -238,16 +238,16 @@ static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data, int sz) { /* XXX Handle access size limits and FW read caching here */ - return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, - data, sz, false); + return !address_space_read(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, + data, sz); } static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data, int sz) { /* XXX Handle access size limits here */ - return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, - data, sz, true); + return !address_space_write(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, + data, sz); } #define ECCB_CTL_READ PPC_BIT(15) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 1a6a8fa..d5ea962 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -909,8 +909,10 @@ static void dcr_write_dma(void *opaque, int dcrn, uint32_t val) sidx = didx = 0; width = 1 << ((val & DMA0_CR_PW) >> 25); - rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen, 0); - wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen, 1); + rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen, + false); + wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen, + true); if (rptr && wptr) { if (!(val & DMA0_CR_DEC) && val & DMA0_CR_SAI && val & DMA0_CR_DAI) { diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 6db3dbd..934eb12 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -832,7 +832,7 @@ static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { return H_PARAMETER; } - pdst = cpu_physical_memory_map(dst, &len, 1); + pdst = cpu_physical_memory_map(dst, &len, true); if (!pdst || len != TARGET_PAGE_SIZE) { return H_PARAMETER; } @@ -843,7 +843,7 @@ static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, ret = H_PARAMETER; goto unmap_out; } - psrc = cpu_physical_memory_map(src, &len, 0); + psrc = cpu_physical_memory_map(src, &len, false); if (!psrc || len != TARGET_PAGE_SIZE) { ret = H_PARAMETER; goto unmap_out; diff --git a/hw/s390x/css.c b/hw/s390x/css.c index 844caab..5d8e086 100644 --- a/hw/s390x/css.c +++ b/hw/s390x/css.c @@ -874,18 +874,18 @@ static inline int ida_read_next_idaw(CcwDataStream *cds) if (idaw_addr & 0x07 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { return -EINVAL; /* channel program check */ } - ret = address_space_rw(&address_space_memory, idaw_addr, - MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt2, - sizeof(idaw.fmt2), false); + ret = address_space_read(&address_space_memory, idaw_addr, + MEMTXATTRS_UNSPECIFIED, &idaw.fmt2, + sizeof(idaw.fmt2)); cds->cda = be64_to_cpu(idaw.fmt2); } else { idaw_addr = cds->cda_orig + sizeof(idaw.fmt1) * cds->at_idaw; if (idaw_addr & 0x03 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { return -EINVAL; /* channel program check */ } - ret = address_space_rw(&address_space_memory, idaw_addr, - MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt1, - sizeof(idaw.fmt1), false); + ret = address_space_read(&address_space_memory, idaw_addr, + MEMTXATTRS_UNSPECIFIED, &idaw.fmt1, + sizeof(idaw.fmt1)); cds->cda = be64_to_cpu(idaw.fmt1); if (cds->cda & 0x80000000) { return -EINVAL; /* channel program check */ diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index 7773499..0817874 100644 --- a/hw/s390x/ipl.c +++ b/hw/s390x/ipl.c @@ -626,7 +626,7 @@ static void s390_ipl_prepare_qipl(S390CPU *cpu) uint8_t *addr; uint64_t len = 4096; - addr = cpu_physical_memory_map(cpu->env.psa, &len, 1); + addr = cpu_physical_memory_map(cpu->env.psa, &len, true); if (!addr || len < QIPL_ADDRESS + sizeof(QemuIplParameters)) { error_report("Cannot set QEMU IPL parameters"); return; diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 7c6a2b3..ed8be12 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -641,7 +641,7 @@ static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set) hwaddr len = 1; uint8_t *ind_addr; - ind_addr = cpu_physical_memory_map(ind_loc, &len, 1); + ind_addr = cpu_physical_memory_map(ind_loc, &len, true); if (!ind_addr) { s390_pci_generate_error_event(ERR_EVENT_AIRERR, 0, 0, 0, 0); return -1; diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c index 13f57e7..50cf95b 100644 --- a/hw/s390x/virtio-ccw.c +++ b/hw/s390x/virtio-ccw.c @@ -790,7 +790,7 @@ static uint8_t virtio_set_ind_atomic(SubchDev *sch, uint64_t ind_loc, hwaddr len = 1; uint8_t *ind_addr; - ind_addr = cpu_physical_memory_map(ind_loc, &len, 1); + ind_addr = cpu_physical_memory_map(ind_loc, &len, true); if (!ind_addr) { error_report("%s(%x.%x.%04x): unable to access indicator", __func__, sch->cssid, sch->ssid, sch->schid); diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index e4ee2e6..c91352c 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -404,8 +404,7 @@ pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc) cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings); trace_pvscsi_cmp_ring_put(cmp_descr_pa); - cpu_physical_memory_write(cmp_descr_pa, (void *)cmp_desc, - sizeof(*cmp_desc)); + cpu_physical_memory_write(cmp_descr_pa, cmp_desc, sizeof(*cmp_desc)); } static void @@ -415,8 +414,7 @@ pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc) msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings); trace_pvscsi_msg_ring_put(msg_descr_pa); - cpu_physical_memory_write(msg_descr_pa, (void *)msg_desc, - sizeof(*msg_desc)); + cpu_physical_memory_write(msg_descr_pa, msg_desc, sizeof(*msg_desc)); } static void @@ -491,7 +489,7 @@ pvscsi_get_next_sg_elem(PVSCSISGState *sg) { struct PVSCSISGElement elem; - cpu_physical_memory_read(sg->elemAddr, (void *)&elem, sizeof(elem)); + cpu_physical_memory_read(sg->elemAddr, &elem, sizeof(elem)); if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) { /* * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 69dc3e6..de63ffb 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -701,8 +701,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr) hwaddr entry_addr = (hwaddr)s->admasysaddr; switch (SDHC_DMA_TYPE(s->hostctl1)) { case SDHC_CTRL_ADMA2_32: - dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2, - sizeof(adma2)); + dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2)); adma2 = le64_to_cpu(adma2); /* The spec does not specify endianness of descriptor table. * We currently assume that it is LE. @@ -713,8 +712,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr) dscr->incr = 8; break; case SDHC_CTRL_ADMA1_32: - dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma1, - sizeof(adma1)); + dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1)); adma1 = le32_to_cpu(adma1); dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); dscr->attr = (uint8_t)extract32(adma1, 0, 7); @@ -726,13 +724,10 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr) } break; case SDHC_CTRL_ADMA2_64: - dma_memory_read(s->dma_as, entry_addr, - (uint8_t *)(&dscr->attr), 1); - dma_memory_read(s->dma_as, entry_addr + 2, - (uint8_t *)(&dscr->length), 2); + dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1); + dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2); dscr->length = le16_to_cpu(dscr->length); - dma_memory_read(s->dma_as, entry_addr + 4, - (uint8_t *)(&dscr->addr), 8); + dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8); dscr->addr = le64_to_cpu(dscr->addr); dscr->attr &= (uint8_t) ~0xC0; dscr->incr = 12; diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c index 9edfadc..0d226da 100644 --- a/hw/virtio/vhost.c +++ b/hw/virtio/vhost.c @@ -294,7 +294,7 @@ static int vhost_dev_has_iommu(struct vhost_dev *dev) } static void *vhost_memory_map(struct vhost_dev *dev, hwaddr addr, - hwaddr *plen, int is_write) + hwaddr *plen, bool is_write) { if (!vhost_dev_has_iommu(dev)) { return cpu_physical_memory_map(addr, plen, is_write); @@ -1012,21 +1012,21 @@ static int vhost_virtqueue_start(struct vhost_dev *dev, vq->desc_size = s = l = virtio_queue_get_desc_size(vdev, idx); vq->desc_phys = a; - vq->desc = vhost_memory_map(dev, a, &l, 0); + vq->desc = vhost_memory_map(dev, a, &l, false); if (!vq->desc || l != s) { r = -ENOMEM; goto fail_alloc_desc; } vq->avail_size = s = l = virtio_queue_get_avail_size(vdev, idx); vq->avail_phys = a = virtio_queue_get_avail_addr(vdev, idx); - vq->avail = vhost_memory_map(dev, a, &l, 0); + vq->avail = vhost_memory_map(dev, a, &l, false); if (!vq->avail || l != s) { r = -ENOMEM; goto fail_alloc_avail; } vq->used_size = s = l = virtio_queue_get_used_size(vdev, idx); vq->used_phys = a = virtio_queue_get_used_addr(vdev, idx); - vq->used = vhost_memory_map(dev, a, &l, 1); + vq->used = vhost_memory_map(dev, a, &l, true); if (!vq->used || l != s) { r = -ENOMEM; goto fail_alloc_used; diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 2c5410e..9d06dbe 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -1293,7 +1293,7 @@ static void virtqueue_undo_map_desc(unsigned int out_num, unsigned int in_num, static void virtqueue_map_iovec(VirtIODevice *vdev, struct iovec *sg, hwaddr *addr, unsigned int num_sg, - int is_write) + bool is_write) { unsigned int i; hwaddr len; @@ -1317,8 +1317,9 @@ static void virtqueue_map_iovec(VirtIODevice *vdev, struct iovec *sg, void virtqueue_map(VirtIODevice *vdev, VirtQueueElement *elem) { - virtqueue_map_iovec(vdev, elem->in_sg, elem->in_addr, elem->in_num, 1); - virtqueue_map_iovec(vdev, elem->out_sg, elem->out_addr, elem->out_num, 0); + virtqueue_map_iovec(vdev, elem->in_sg, elem->in_addr, elem->in_num, true); + virtqueue_map_iovec(vdev, elem->out_sg, elem->out_addr, elem->out_num, + false); } static void *virtqueue_alloc_element(size_t sz, unsigned out_num, unsigned in_num) diff --git a/hw/xen/xen_pt_graphics.c b/hw/xen/xen_pt_graphics.c index b697327..a3bc7e3 100644 --- a/hw/xen/xen_pt_graphics.c +++ b/hw/xen/xen_pt_graphics.c @@ -222,7 +222,7 @@ void xen_pt_setup_vga(XenPCIPassthroughState *s, XenHostPCIDevice *dev, } /* Currently we fixed this address as a primary for legacy BIOS. */ - cpu_physical_memory_rw(0xc0000, bios, bios_size, 1); + cpu_physical_memory_write(0xc0000, bios, bios_size); } uint32_t igd_read_opregion(XenPCIPassthroughState *s) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index e96781a..49384bb 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -388,7 +388,7 @@ void dump_opcount_info(void); #endif /* !CONFIG_USER_ONLY */ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, - uint8_t *buf, target_ulong len, int is_write); + void *ptr, target_ulong len, bool is_write); int cpu_exec(CPUState *cpu); diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 81753bb..b47e563 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -69,23 +69,23 @@ void qemu_ram_unset_migratable(RAMBlock *rb); size_t qemu_ram_pagesize(RAMBlock *block); size_t qemu_ram_pagesize_largest(void); -void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, - hwaddr len, int is_write); +void cpu_physical_memory_rw(hwaddr addr, void *buf, + hwaddr len, bool is_write); static inline void cpu_physical_memory_read(hwaddr addr, void *buf, hwaddr len) { - cpu_physical_memory_rw(addr, buf, len, 0); + cpu_physical_memory_rw(addr, buf, len, false); } static inline void cpu_physical_memory_write(hwaddr addr, const void *buf, hwaddr len) { - cpu_physical_memory_rw(addr, (void *)buf, len, 1); + cpu_physical_memory_rw(addr, (void *)buf, len, true); } void *cpu_physical_memory_map(hwaddr addr, hwaddr *plen, - int is_write); + bool is_write); void cpu_physical_memory_unmap(void *buffer, hwaddr len, - int is_write, hwaddr access_len); + bool is_write, hwaddr access_len); void cpu_register_map_client(QEMUBH *bh); void cpu_unregister_map_client(QEMUBH *bh); diff --git a/include/exec/memory.h b/include/exec/memory.h index e85b7de..1614d9a 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -2052,7 +2052,7 @@ void address_space_remove_listeners(AddressSpace *as); * @is_write: indicates the transfer direction */ MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, + MemTxAttrs attrs, void *buf, hwaddr len, bool is_write); /** @@ -2070,7 +2070,7 @@ MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, */ MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, hwaddr len); + const void *buf, hwaddr len); /** * address_space_write_rom: write to address space, including ROM. @@ -2096,7 +2096,7 @@ MemTxResult address_space_write(AddressSpace *as, hwaddr addr, */ MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, hwaddr len); + const void *buf, hwaddr len); /* address_space_ld*: load from an address space * address_space_st*: store to an address space @@ -2329,14 +2329,14 @@ void *address_space_map(AddressSpace *as, hwaddr addr, * @is_write: indicates the transfer direction */ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, - int is_write, hwaddr access_len); + bool is_write, hwaddr access_len); /* Internal functions, part of the implementation of address_space_read. */ MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, hwaddr len); + MemTxAttrs attrs, void *buf, hwaddr len); MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, + MemTxAttrs attrs, void *buf, hwaddr len, hwaddr addr1, hwaddr l, MemoryRegion *mr); void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr); @@ -2374,7 +2374,7 @@ static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write) */ static inline __attribute__((__always_inline__)) MemTxResult address_space_read(AddressSpace *as, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, + MemTxAttrs attrs, void *buf, hwaddr len) { MemTxResult result = MEMTX_OK; @@ -2433,7 +2433,7 @@ address_space_read_cached(MemoryRegionCache *cache, hwaddr addr, */ static inline void address_space_write_cached(MemoryRegionCache *cache, hwaddr addr, - void *buf, hwaddr len) + const void *buf, hwaddr len) { assert(addr < cache->len && len <= cache->len - addr); if (likely(cache->ptr)) { diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h index 52ec197..1bc1fc7 100644 --- a/include/hw/ide/internal.h +++ b/include/hw/ide/internal.h @@ -322,11 +322,10 @@ typedef void EndTransferFunc(IDEState *); typedef void DMAStartFunc(IDEDMA *, IDEState *, BlockCompletionFunc *); typedef void DMAVoidFunc(IDEDMA *); -typedef int DMAIntFunc(IDEDMA *, int); +typedef int DMAIntFunc(IDEDMA *, bool); typedef int32_t DMAInt32Func(IDEDMA *, int32_t len); typedef void DMAu32Func(IDEDMA *, uint32_t); typedef void DMAStopFunc(IDEDMA *, bool); -typedef void DMARestartFunc(void *, int, RunState); struct unreported_events { bool eject_request; @@ -434,23 +434,23 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (words[0][5] == 'b') { uint8_t data = value; - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - &data, 1, true); + address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &data, 1); } else if (words[0][5] == 'w') { uint16_t data = value; tswap16s(&data); - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *) &data, 2, true); + address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &data, 2); } else if (words[0][5] == 'l') { uint32_t data = value; tswap32s(&data); - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *) &data, 4, true); + address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &data, 4); } else if (words[0][5] == 'q') { uint64_t data = value; tswap64s(&data); - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *) &data, 8, true); + address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &data, 8); } qtest_send_prefix(chr); qtest_send(chr, "OK\n"); @@ -468,22 +468,22 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (words[0][4] == 'b') { uint8_t data; - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - &data, 1, false); + address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &data, 1); value = data; } else if (words[0][4] == 'w') { uint16_t data; - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *) &data, 2, false); + address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &data, 2); value = tswap16(data); } else if (words[0][4] == 'l') { uint32_t data; - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *) &data, 4, false); + address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &data, 4); value = tswap32(data); } else if (words[0][4] == 'q') { - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *) &value, 8, false); + address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &value, 8); tswap64s(&value); } qtest_send_prefix(chr); @@ -503,8 +503,8 @@ static void qtest_process_command(CharBackend *chr, gchar **words) g_assert(len); data = g_malloc(len); - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - data, len, false); + address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + len); enc = g_malloc(2 * len + 1); for (i = 0; i < len; i++) { @@ -529,8 +529,8 @@ static void qtest_process_command(CharBackend *chr, gchar **words) g_assert(ret == 0); data = g_malloc(len); - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - data, len, false); + address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + len); b64_data = g_base64_encode(data, len); qtest_send_prefix(chr); qtest_sendf(chr, "OK %s\n", b64_data); @@ -564,8 +564,8 @@ static void qtest_process_command(CharBackend *chr, gchar **words) data[i] = 0; } } - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - data, len, true); + address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + len); g_free(data); qtest_send_prefix(chr); @@ -587,8 +587,8 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (len) { data = g_malloc(len); memset(data, pattern, len); - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - data, len, true); + address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + data, len); g_free(data); } @@ -621,8 +621,8 @@ static void qtest_process_command(CharBackend *chr, gchar **words) out_len = MIN(out_len, len); } - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - data, len, true); + address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + len); qtest_send_prefix(chr); qtest_send(chr, "OK\n"); diff --git a/scripts/coccinelle/exec_rw_const.cocci b/scripts/coccinelle/exec_rw_const.cocci new file mode 100644 index 0000000..1a20296 --- /dev/null +++ b/scripts/coccinelle/exec_rw_const.cocci @@ -0,0 +1,111 @@ +/* + Usage: + + spatch \ + --macro-file scripts/cocci-macro-file.h \ + --sp-file scripts/coccinelle/exec_rw_const.cocci \ + --keep-comments \ + --in-place \ + --dir . +*/ + +// Convert to boolean +@@ +expression E1, E2, E3, E4, E5; +@@ +( +- address_space_rw(E1, E2, E3, E4, E5, 0) ++ address_space_rw(E1, E2, E3, E4, E5, false) +| +- address_space_rw(E1, E2, E3, E4, E5, 1) ++ address_space_rw(E1, E2, E3, E4, E5, true) +| + +- cpu_physical_memory_rw(E1, E2, E3, 0) ++ cpu_physical_memory_rw(E1, E2, E3, false) +| +- cpu_physical_memory_rw(E1, E2, E3, 1) ++ cpu_physical_memory_rw(E1, E2, E3, true) +| + +- cpu_physical_memory_map(E1, E2, 0) ++ cpu_physical_memory_map(E1, E2, false) +| +- cpu_physical_memory_map(E1, E2, 1) ++ cpu_physical_memory_map(E1, E2, true) +) + +// Use address_space_write instead of casting to non-const +@@ +type T; +const T *V; +expression E1, E2, E3, E4; +@@ +( +- address_space_rw(E1, E2, E3, (T *)V, E4, 1) ++ address_space_write(E1, E2, E3, V, E4) +| +- address_space_rw(E1, E2, E3, (void *)V, E4, 1) ++ address_space_write(E1, E2, E3, V, E4) +) + +// Avoid uses of address_space_rw() with a constant is_write argument. +@@ +expression E1, E2, E3, E4, E5; +symbol true, false; +@@ +( +- address_space_rw(E1, E2, E3, E4, E5, false) ++ address_space_read(E1, E2, E3, E4, E5) +| +- address_space_rw(E1, E2, E3, E4, E5, true) ++ address_space_write(E1, E2, E3, E4, E5) +) + +// Avoid uses of cpu_physical_memory_rw() with a constant is_write argument. +@@ +expression E1, E2, E3; +@@ +( +- cpu_physical_memory_rw(E1, E2, E3, false) ++ cpu_physical_memory_read(E1, E2, E3) +| +- cpu_physical_memory_rw(E1, E2, E3, true) ++ cpu_physical_memory_write(E1, E2, E3) +) + +// Remove useless cast +@@ +expression E1, E2, E3, E4, E5, E6; +type T; +@@ +( +- address_space_rw(E1, E2, E3, (T *)(E4), E5, E6) ++ address_space_rw(E1, E2, E3, E4, E5, E6) +| +- address_space_read(E1, E2, E3, (T *)(E4), E5) ++ address_space_read(E1, E2, E3, E4, E5) +| +- address_space_write(E1, E2, E3, (T *)(E4), E5) ++ address_space_write(E1, E2, E3, E4, E5) +| +- address_space_write_rom(E1, E2, E3, (T *)(E4), E5) ++ address_space_write_rom(E1, E2, E3, E4, E5) +| + +- cpu_physical_memory_rw(E1, (T *)(E2), E3, E4) ++ cpu_physical_memory_rw(E1, E2, E3, E4) +| +- cpu_physical_memory_read(E1, (T *)(E2), E3) ++ cpu_physical_memory_read(E1, E2, E3) +| +- cpu_physical_memory_write(E1, (T *)(E2), E3) ++ cpu_physical_memory_write(E1, E2, E3) +| + +- dma_memory_read(E1, E2, (T *)(E3), E4) ++ dma_memory_read(E1, E2, E3, E4) +| +- dma_memory_write(E1, E2, (T *)(E3), E4) ++ dma_memory_write(E1, E2, E3, E4) +) diff --git a/scripts/git.orderfile b/scripts/git.orderfile index 1f747b5..7cf22e0 100644 --- a/scripts/git.orderfile +++ b/scripts/git.orderfile @@ -22,6 +22,9 @@ Makefile* qapi/*.json qga/*.json +# semantic patches +*.cocci + # headers *.h diff --git a/target/i386/hax-all.c b/target/i386/hax-all.c index a8b6e5a..f9c83ff 100644 --- a/target/i386/hax-all.c +++ b/target/i386/hax-all.c @@ -367,7 +367,7 @@ static int hax_accel_init(MachineState *ms) static int hax_handle_fastmmio(CPUArchState *env, struct hax_fastmmio *hft) { if (hft->direction < 2) { - cpu_physical_memory_rw(hft->gpa, (uint8_t *) &hft->value, hft->size, + cpu_physical_memory_rw(hft->gpa, &hft->value, hft->size, hft->direction); } else { /* @@ -376,8 +376,8 @@ static int hax_handle_fastmmio(CPUArchState *env, struct hax_fastmmio *hft) * hft->direction == 2: gpa ==> gpa2 */ uint64_t value; - cpu_physical_memory_rw(hft->gpa, (uint8_t *) &value, hft->size, 0); - cpu_physical_memory_rw(hft->gpa2, (uint8_t *) &value, hft->size, 1); + cpu_physical_memory_read(hft->gpa, &value, hft->size); + cpu_physical_memory_write(hft->gpa2, &value, hft->size); } return 0; diff --git a/target/i386/hvf/vmx.h b/target/i386/hvf/vmx.h index eb8894c..03d2c79 100644 --- a/target/i386/hvf/vmx.h +++ b/target/i386/hvf/vmx.h @@ -125,10 +125,9 @@ static inline void macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0) if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) && !(efer & MSR_EFER_LME)) { - address_space_rw(&address_space_memory, - rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f, - MEMTXATTRS_UNSPECIFIED, - (uint8_t *)pdpte, 32, 0); + address_space_read(&address_space_memory, + rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f, + MEMTXATTRS_UNSPECIFIED, pdpte, 32); /* Only set PDPTE when appropriate. */ for (i = 0; i < 4; i++) { wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]); diff --git a/target/i386/hvf/x86_mmu.c b/target/i386/hvf/x86_mmu.c index d5a0efe..65d4603 100644 --- a/target/i386/hvf/x86_mmu.c +++ b/target/i386/hvf/x86_mmu.c @@ -88,8 +88,8 @@ static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, } index = gpt_entry(pt->gva, level, pae); - address_space_rw(&address_space_memory, gpa + index * pte_size(pae), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)&pte, pte_size(pae), 0); + address_space_read(&address_space_memory, gpa + index * pte_size(pae), + MEMTXATTRS_UNSPECIFIED, &pte, pte_size(pae)); pt->pte[level - 1] = pte; @@ -238,8 +238,8 @@ void vmx_write_mem(struct CPUState *cpu, target_ulong gva, void *data, int bytes if (!mmu_gva_to_gpa(cpu, gva, &gpa)) { VM_PANIC_EX("%s: mmu_gva_to_gpa %llx failed\n", __func__, gva); } else { - address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, - data, copy, 1); + address_space_write(&address_space_memory, gpa, + MEMTXATTRS_UNSPECIFIED, data, copy); } bytes -= copy; @@ -259,8 +259,8 @@ void vmx_read_mem(struct CPUState *cpu, void *data, target_ulong gva, int bytes) if (!mmu_gva_to_gpa(cpu, gva, &gpa)) { VM_PANIC_EX("%s: mmu_gva_to_gpa %llx failed\n", __func__, gva); } - address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, - data, copy, 0); + address_space_read(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, + data, copy); bytes -= copy; gva += copy; diff --git a/target/i386/whpx-all.c b/target/i386/whpx-all.c index 35601b8..683d49d 100644 --- a/target/i386/whpx-all.c +++ b/target/i386/whpx-all.c @@ -540,7 +540,7 @@ static HRESULT CALLBACK whpx_emu_ioport_callback( { MemTxAttrs attrs = { 0 }; address_space_rw(&address_space_io, IoAccess->Port, attrs, - (uint8_t *)&IoAccess->Data, IoAccess->AccessSize, + &IoAccess->Data, IoAccess->AccessSize, IoAccess->Direction); return S_OK; } diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index 1e9d6f2..3b58d10 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -393,7 +393,7 @@ static int mchk_store_vregs(CPUS390XState *env, uint64_t mcesao) MchkExtSaveArea *sa; int i; - sa = cpu_physical_memory_map(mcesao, &len, 1); + sa = cpu_physical_memory_map(mcesao, &len, true); if (!sa) { return -EFAULT; } diff --git a/target/s390x/helper.c b/target/s390x/helper.c index a3a4916..b810ad4 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -151,7 +151,7 @@ LowCore *cpu_map_lowcore(CPUS390XState *env) LowCore *lowcore; hwaddr len = sizeof(LowCore); - lowcore = cpu_physical_memory_map(env->psa, &len, 1); + lowcore = cpu_physical_memory_map(env->psa, &len, true); if (len < sizeof(LowCore)) { cpu_abort(env_cpu(env), "Could not map lowcore\n"); @@ -246,7 +246,7 @@ int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch) hwaddr len = sizeof(*sa); int i; - sa = cpu_physical_memory_map(addr, &len, 1); + sa = cpu_physical_memory_map(addr, &len, true); if (!sa) { return -EFAULT; } @@ -298,7 +298,7 @@ int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len) hwaddr save = len; int i; - sa = cpu_physical_memory_map(addr, &save, 1); + sa = cpu_physical_memory_map(addr, &save, true); if (!sa) { return -EFAULT; } diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index c9f3f34..0be2f30 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -106,7 +106,7 @@ static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr, * We treat them as absolute addresses and don't wrap them. */ if (unlikely(address_space_read(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *)entry, sizeof(*entry)) != + entry, sizeof(*entry)) != MEMTX_OK)) { return false; } |