diff options
| -rw-r--r-- | MAINTAINERS | 4 | ||||
| -rw-r--r-- | hw/intc/arm_gicv3_cpuif.c | 3 |
2 files changed, 3 insertions, 4 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index caba73e..be151f0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1748,8 +1748,8 @@ F: tests/qtest/intel-hda-test.c F: tests/qtest/fuzz-sb16-test.c Xilinx CAN -M: Vikram Garhwal <fnu.vikram@xilinx.com> -M: Francisco Iglesias <francisco.iglesias@xilinx.com> +M: Vikram Garhwal <vikram.garhwal@amd.com> +M: Francisco Iglesias <francisco.iglesias@amd.com> S: Maintained F: hw/net/can/xlnx-* F: include/hw/net/xlnx-* diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 8ca630e..b17b292 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1016,8 +1016,6 @@ static void icc_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs), value); - value &= icc_fullprio_mask(cs); - if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) && (env->cp15.scr_el3 & SCR_FIQ)) { /* NS access and Group 0 is inaccessible to NS: return the @@ -1029,6 +1027,7 @@ static void icc_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, } value = (value >> 1) | 0x80; } + value &= icc_fullprio_mask(cs); cs->icc_pmr_el1 = value; gicv3_cpuif_update(cs); } |