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| author | Stefan Hajnoczi <stefanha@redhat.com> | 2022-11-14 13:31:17 -0500 |
|---|---|---|
| committer | Stefan Hajnoczi <stefanha@redhat.com> | 2022-11-14 13:31:17 -0500 |
| commit | 98f10f0e2613ba1ac2ad3f57a5174014f6dcb03d (patch) | |
| tree | ebbd542126edded7e8221816f87d5bd50ae59114 | |
| parent | 305f6f62d9d250a32cdf090ddcb7e3a5b26a342e (diff) | |
| parent | d9721f19cd05a382f4f5a7093c80d1c4a8a1aa82 (diff) | |
| download | qemu-98f10f0e2613ba1ac2ad3f57a5174014f6dcb03d.zip qemu-98f10f0e2613ba1ac2ad3f57a5174014f6dcb03d.tar.gz qemu-98f10f0e2613ba1ac2ad3f57a5174014f6dcb03d.tar.bz2 | |
Merge tag 'pull-target-arm-20221114' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/intc/arm_gicv3: fix prio masking on pmr write
* MAINTAINERS: Update maintainer's email for Xilinx CAN
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# gpg: Signature made Mon 14 Nov 2022 10:50:15 EST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20221114' of https://git.linaro.org/people/pmaydell/qemu-arm:
hw/intc/arm_gicv3: fix prio masking on pmr write
MAINTAINERS: Update maintainer's email for Xilinx CAN
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| -rw-r--r-- | MAINTAINERS | 4 | ||||
| -rw-r--r-- | hw/intc/arm_gicv3_cpuif.c | 3 |
2 files changed, 3 insertions, 4 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index caba73e..be151f0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1748,8 +1748,8 @@ F: tests/qtest/intel-hda-test.c F: tests/qtest/fuzz-sb16-test.c Xilinx CAN -M: Vikram Garhwal <fnu.vikram@xilinx.com> -M: Francisco Iglesias <francisco.iglesias@xilinx.com> +M: Vikram Garhwal <vikram.garhwal@amd.com> +M: Francisco Iglesias <francisco.iglesias@amd.com> S: Maintained F: hw/net/can/xlnx-* F: include/hw/net/xlnx-* diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 8ca630e..b17b292 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1016,8 +1016,6 @@ static void icc_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs), value); - value &= icc_fullprio_mask(cs); - if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) && (env->cp15.scr_el3 & SCR_FIQ)) { /* NS access and Group 0 is inaccessible to NS: return the @@ -1029,6 +1027,7 @@ static void icc_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, } value = (value >> 1) | 0x80; } + value &= icc_fullprio_mask(cs); cs->icc_pmr_el1 = value; gicv3_cpuif_update(cs); } |