diff options
-rw-r--r-- | target-i386/cc_helper.c | 10 | ||||
-rw-r--r-- | target-i386/helper.h | 2 | ||||
-rw-r--r-- | target-i386/translate.c | 37 |
3 files changed, 28 insertions, 21 deletions
diff --git a/target-i386/cc_helper.c b/target-i386/cc_helper.c index 99a3b54..83af223 100644 --- a/target-i386/cc_helper.c +++ b/target-i386/cc_helper.c @@ -383,13 +383,3 @@ void helper_sti_vm(CPUX86State *env) } } #endif - -void helper_set_inhibit_irq(CPUX86State *env) -{ - env->hflags |= HF_INHIBIT_IRQ_MASK; -} - -void helper_reset_inhibit_irq(CPUX86State *env) -{ - env->hflags &= ~HF_INHIBIT_IRQ_MASK; -} diff --git a/target-i386/helper.h b/target-i386/helper.h index 9a83955..14a5041 100644 --- a/target-i386/helper.h +++ b/target-i386/helper.h @@ -62,8 +62,6 @@ DEF_HELPER_1(cli, void, env) DEF_HELPER_1(sti, void, env) DEF_HELPER_1(clac, void, env) DEF_HELPER_1(stac, void, env) -DEF_HELPER_1(set_inhibit_irq, void, env) -DEF_HELPER_1(reset_inhibit_irq, void, env) DEF_HELPER_3(boundw, void, env, tl, int) DEF_HELPER_3(boundl, void, env, tl, int) DEF_HELPER_1(rsm, void, env) diff --git a/target-i386/translate.c b/target-i386/translate.c index dc87e58..cb25354 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -2391,14 +2391,36 @@ static void gen_debug(DisasContext *s, target_ulong cur_eip) s->is_jmp = DISAS_TB_JUMP; } +static void gen_set_hflag(DisasContext *s, uint32_t mask) +{ + if ((s->flags & mask) == 0) { + TCGv_i32 t = tcg_temp_new_i32(); + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags)); + tcg_gen_ori_i32(t, t, mask); + tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags)); + tcg_temp_free_i32(t); + s->flags |= mask; + } +} + +static void gen_reset_hflag(DisasContext *s, uint32_t mask) +{ + if (s->flags & mask) { + TCGv_i32 t = tcg_temp_new_i32(); + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags)); + tcg_gen_andi_i32(t, t, ~mask); + tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags)); + tcg_temp_free_i32(t); + s->flags &= ~mask; + } +} + /* generate a generic end of block. Trace exception is also generated if needed */ static void gen_eob(DisasContext *s) { gen_update_cc_op(s); - if (s->tb->flags & HF_INHIBIT_IRQ_MASK) { - gen_helper_reset_inhibit_irq(cpu_env); - } + gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK); if (s->tb->flags & HF_RF_MASK) { gen_helper_reset_rf(cpu_env); } @@ -5147,8 +5169,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* if reg == SS, inhibit interrupts/trace. */ /* If several instructions disable interrupts, only the _first_ does it */ - if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) - gen_helper_set_inhibit_irq(cpu_env); + gen_set_hflag(s, HF_INHIBIT_IRQ_MASK); s->tf = 0; } if (s->is_jmp) { @@ -5215,8 +5236,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* if reg == SS, inhibit interrupts/trace */ /* If several instructions disable interrupts, only the _first_ does it */ - if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) - gen_helper_set_inhibit_irq(cpu_env); + gen_set_hflag(s, HF_INHIBIT_IRQ_MASK); s->tf = 0; } if (s->is_jmp) { @@ -6752,8 +6772,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* interruptions are enabled only the first insn after sti */ /* If several instructions disable interrupts, only the _first_ does it */ - if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) - gen_helper_set_inhibit_irq(cpu_env); + gen_set_hflag(s, HF_INHIBIT_IRQ_MASK); /* give a chance to handle pending irqs */ gen_jmp_im(s->pc - s->cs_base); gen_eob(s); |