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| -rw-r--r-- | MAINTAINERS | 1 | ||||
| -rw-r--r-- | docs/system/arm/xlnx-zcu102.rst | 19 | ||||
| -rw-r--r-- | docs/system/target-arm.rst | 1 |
3 files changed, 21 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 2b524d7..66c7572 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1018,6 +1018,7 @@ F: include/hw/ssi/xilinx_spips.h F: hw/display/dpcd.c F: include/hw/display/dpcd.h F: docs/system/arm/xlnx-versal-virt.rst +F: docs/system/arm/xlnx-zcu102.rst Xilinx Versal OSPI M: Francisco Iglesias <francisco.iglesias@amd.com> diff --git a/docs/system/arm/xlnx-zcu102.rst b/docs/system/arm/xlnx-zcu102.rst new file mode 100644 index 0000000..534cd1d --- /dev/null +++ b/docs/system/arm/xlnx-zcu102.rst @@ -0,0 +1,19 @@ +Xilinx ZynqMP ZCU102 (``xlnx-zcu102``) +====================================== + +The ``xlnx-zcu102`` board models the Xilinx ZynqMP ZCU102 board. +This board has 4 Cortex-A53 CPUs and 2 Cortex-R5F CPUs. + +Machine-specific options +"""""""""""""""""""""""" + +The following machine-specific options are supported: + +secure + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the + Arm Security Extensions (TrustZone). The default is ``off``. + +virtualization + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the + Arm Virtualization Extensions. The default is ``off``. + diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index a7f88c8..ace36d1 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -107,6 +107,7 @@ undocumented; you can get a complete list by running arm/xenpvh arm/xlnx-versal-virt arm/xlnx-zynq + arm/xlnx-zcu102 Emulated CPU architecture support ================================= |