diff options
| -rw-r--r-- | hw/ssi/aspeed_smc.c | 53 | ||||
| -rw-r--r-- | include/hw/ssi/aspeed_smc.h | 2 |
2 files changed, 28 insertions, 27 deletions
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index e3d5e26..16addee 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -191,7 +191,7 @@ #define SNOOP_START 0x0 /* - * Default segments mapping addresses and size for each slave per + * Default segments mapping addresses and size for each peripheral per * controller. These can be changed when board is initialized with the * Segment Address Registers. */ @@ -269,7 +269,7 @@ static const AspeedSMCController controllers[] = { .r_timings = R_TIMINGS, .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, - .max_slaves = 1, + .max_peripherals = 1, .segments = aspeed_segments_legacy, .flash_window_base = ASPEED_SOC_SMC_FLASH_BASE, .flash_window_size = 0x6000000, @@ -285,7 +285,7 @@ static const AspeedSMCController controllers[] = { .r_timings = R_TIMINGS, .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, - .max_slaves = 5, + .max_peripherals = 5, .segments = aspeed_segments_fmc, .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE, .flash_window_size = 0x10000000, @@ -303,7 +303,7 @@ static const AspeedSMCController controllers[] = { .r_timings = R_SPI_TIMINGS, .nregs_timings = 1, .conf_enable_w0 = SPI_CONF_ENABLE_W0, - .max_slaves = 1, + .max_peripherals = 1, .segments = aspeed_segments_spi, .flash_window_base = ASPEED_SOC_SPI_FLASH_BASE, .flash_window_size = 0x10000000, @@ -319,7 +319,7 @@ static const AspeedSMCController controllers[] = { .r_timings = R_TIMINGS, .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, - .max_slaves = 3, + .max_peripherals = 3, .segments = aspeed_segments_ast2500_fmc, .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE, .flash_window_size = 0x10000000, @@ -337,7 +337,7 @@ static const AspeedSMCController controllers[] = { .r_timings = R_TIMINGS, .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, - .max_slaves = 2, + .max_peripherals = 2, .segments = aspeed_segments_ast2500_spi1, .flash_window_base = ASPEED_SOC_SPI_FLASH_BASE, .flash_window_size = 0x8000000, @@ -353,7 +353,7 @@ static const AspeedSMCController controllers[] = { .r_timings = R_TIMINGS, .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, - .max_slaves = 2, + .max_peripherals = 2, .segments = aspeed_segments_ast2500_spi2, .flash_window_base = ASPEED_SOC_SPI2_FLASH_BASE, .flash_window_size = 0x8000000, @@ -369,7 +369,7 @@ static const AspeedSMCController controllers[] = { .r_timings = R_TIMINGS, .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, - .max_slaves = 3, + .max_peripherals = 3, .segments = aspeed_segments_ast2600_fmc, .flash_window_base = ASPEED26_SOC_FMC_FLASH_BASE, .flash_window_size = 0x10000000, @@ -387,7 +387,7 @@ static const AspeedSMCController controllers[] = { .r_timings = R_TIMINGS, .nregs_timings = 2, .conf_enable_w0 = CONF_ENABLE_W0, - .max_slaves = 2, + .max_peripherals = 2, .segments = aspeed_segments_ast2600_spi1, .flash_window_base = ASPEED26_SOC_SPI_FLASH_BASE, .flash_window_size = 0x10000000, @@ -405,7 +405,7 @@ static const AspeedSMCController controllers[] = { .r_timings = R_TIMINGS, .nregs_timings = 3, .conf_enable_w0 = CONF_ENABLE_W0, - .max_slaves = 3, + .max_peripherals = 3, .segments = aspeed_segments_ast2600_spi2, .flash_window_base = ASPEED26_SOC_SPI2_FLASH_BASE, .flash_window_size = 0x10000000, @@ -420,7 +420,7 @@ static const AspeedSMCController controllers[] = { /* * The Segment Registers of the AST2400 and AST2500 have a 8MB - * unit. The address range of a flash SPI slave is encoded with + * unit. The address range of a flash SPI peripheral is encoded with * absolute addresses which should be part of the overall controller * window. */ @@ -442,7 +442,7 @@ static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, /* * The Segment Registers of the AST2600 have a 1MB unit. The address - * range of a flash SPI slave is encoded with offsets in the overall + * range of a flash SPI peripheral is encoded with offsets in the overall * controller window. The previous SoC AST2400 and AST2500 used * absolute addresses. Only bits [27:20] are relevant and the end * address is an upper bound limit. @@ -486,7 +486,7 @@ static bool aspeed_smc_flash_overlap(const AspeedSMCState *s, AspeedSegments seg; int i; - for (i = 0; i < s->ctrl->max_slaves; i++) { + for (i = 0; i < s->ctrl->max_peripherals; i++) { if (i == cs) { continue; } @@ -547,7 +547,7 @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, */ if ((s->ctrl->segments == aspeed_segments_ast2500_spi1 || s->ctrl->segments == aspeed_segments_ast2500_spi2) && - cs == s->ctrl->max_slaves && + cs == s->ctrl->max_peripherals && seg.addr + seg.size != s->ctrl->segments[cs].addr + s->ctrl->segments[cs].size) { qemu_log_mask(LOG_GUEST_ERROR, @@ -949,14 +949,14 @@ static void aspeed_smc_reset(DeviceState *d) memset(s->regs, 0, sizeof s->regs); - /* Unselect all slaves */ + /* Unselect all peripherals */ for (i = 0; i < s->num_cs; ++i) { s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE; qemu_set_irq(s->cs_lines[i], true); } /* setup the default segment register values and regions for all */ - for (i = 0; i < s->ctrl->max_slaves; ++i) { + for (i = 0; i < s->ctrl->max_peripherals; ++i) { aspeed_smc_flash_set_segment_region(s, i, s->ctrl->segment_to_reg(s, &s->ctrl->segments[i])); } @@ -1004,8 +1004,9 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) || (s->ctrl->has_dma && addr == R_DMA_LEN) || (s->ctrl->has_dma && addr == R_DMA_CHECKSUM) || - (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) || - (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) { + (addr >= R_SEG_ADDR0 && + addr < R_SEG_ADDR0 + s->ctrl->max_peripherals) || + (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_peripherals)) { trace_aspeed_smc_read(addr, size, s->regs[addr]); @@ -1279,7 +1280,7 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, int cs = addr - s->r_ctrl0; aspeed_smc_flash_update_ctrl(&s->flashes[cs], value); } else if (addr >= R_SEG_ADDR0 && - addr < R_SEG_ADDR0 + s->ctrl->max_slaves) { + addr < R_SEG_ADDR0 + s->ctrl->max_peripherals) { int cs = addr - R_SEG_ADDR0; if (value != s->regs[R_SEG_ADDR0 + cs]) { @@ -1352,10 +1353,10 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) s->conf_enable_w0 = s->ctrl->conf_enable_w0; /* Enforce some real HW limits */ - if (s->num_cs > s->ctrl->max_slaves) { + if (s->num_cs > s->ctrl->max_peripherals) { qemu_log_mask(LOG_GUEST_ERROR, "%s: num_cs cannot exceed: %d\n", - __func__, s->ctrl->max_slaves); - s->num_cs = s->ctrl->max_slaves; + __func__, s->ctrl->max_peripherals); + s->num_cs = s->ctrl->max_peripherals; } /* DMA irq. Keep it first for the initialization in the SoC */ @@ -1363,7 +1364,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) s->spi = ssi_create_bus(dev, "spi"); - /* Setup cs_lines for slaves */ + /* Setup cs_lines for peripherals */ s->cs_lines = g_new0(qemu_irq, s->num_cs); for (i = 0; i < s->num_cs; ++i) { @@ -1387,16 +1388,16 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) s->ctrl->flash_window_size); sysbus_init_mmio(sbd, &s->mmio_flash); - s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_slaves); + s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_peripherals); /* - * Let's create a sub memory region for each possible slave. All + * Let's create a sub memory region for each possible peripheral. All * have a configurable memory segment in the overall flash mapping * window of the controller but, there is not necessarily a flash * module behind to handle the memory accesses. This depends on * the board configuration. */ - for (i = 0; i < s->ctrl->max_slaves; ++i) { + for (i = 0; i < s->ctrl->max_peripherals; ++i) { AspeedSMCFlash *fl = &s->flashes[i]; snprintf(name, sizeof(name), "%s.%d", s->ctrl->name, i); diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 3dd354b..16c03fe 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -43,7 +43,7 @@ typedef struct AspeedSMCController { uint8_t r_timings; uint8_t nregs_timings; uint8_t conf_enable_w0; - uint8_t max_slaves; + uint8_t max_peripherals; const AspeedSegments *segments; hwaddr flash_window_base; uint32_t flash_window_size; |