diff options
| -rw-r--r-- | hw/arm/xlnx-zynqmp.c | 24 | ||||
| -rw-r--r-- | include/hw/arm/xlnx-zynqmp.h | 3 |
2 files changed, 27 insertions, 0 deletions
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 456dea0..6b01965 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -36,6 +36,14 @@ static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 57, 59, 61, 63, }; +static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { + 0xFF000000, 0xFF010000, +}; + +static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { + 21, 22, +}; + typedef struct XlnxZynqMPGICRegion { int region_index; uint32_t address; @@ -70,6 +78,11 @@ static void xlnx_zynqmp_init(Object *obj) object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM); qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default()); } + + for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { + object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART); + qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); + } } static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) @@ -162,6 +175,17 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, gic_spi[gem_intr[i]]); } + + for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { + object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); + if (err) { + error_propagate((errp), (err)); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + gic_spi[uart_intr[i]]); + } } static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index c6ccbd8..79c2b0b 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -21,6 +21,7 @@ #include "hw/arm/arm.h" #include "hw/intc/arm_gic.h" #include "hw/net/cadence_gem.h" +#include "hw/char/cadence_uart.h" #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ @@ -28,6 +29,7 @@ #define XLNX_ZYNQMP_NUM_CPUS 4 #define XLNX_ZYNQMP_NUM_GEMS 4 +#define XLNX_ZYNQMP_NUM_UARTS 2 #define XLNX_ZYNQMP_GIC_REGIONS 2 @@ -49,6 +51,7 @@ typedef struct XlnxZynqMPState { GICState gic; MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; + CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; } XlnxZynqMPState; #define XLNX_ZYNQMP_H |