diff options
| -rw-r--r-- | target/riscv/cpu.c | 10 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 8 | ||||
| -rw-r--r-- | target/riscv/csr.c | 8 |
3 files changed, 23 insertions, 3 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 78fc7b2..cfdfe78 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -708,7 +708,6 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level) case IRQ_VS_TIMER: case IRQ_M_TIMER: case IRQ_U_EXT: - case IRQ_S_EXT: case IRQ_VS_EXT: case IRQ_M_EXT: if (kvm_enabled()) { @@ -717,6 +716,15 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level) riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); } break; + case IRQ_S_EXT: + if (kvm_enabled()) { + kvm_riscv_set_irq(cpu, irq, level); + } else { + env->external_seip = level; + riscv_cpu_update_mip(cpu, 1 << irq, + BOOL_TO_MASK(level | env->software_seip)); + } + break; default: g_assert_not_reached(); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e129c3d..b90ca82 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -177,6 +177,14 @@ struct CPUArchState { uint64_t mstatus; uint64_t mip; + /* + * MIP contains the software writable version of SEIP ORed with the + * external interrupt value. The MIP register is always up-to-date. + * To keep track of the current source, we also save booleans of the values + * here. + */ + bool external_seip; + bool software_seip; uint64_t miclaim; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8b6a1b9..a09126a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1498,10 +1498,14 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno, uint64_t new_val, uint64_t wr_mask) { RISCVCPU *cpu = env_archcpu(env); - /* Allow software control of delegable interrupts not claimed by hardware */ - uint64_t old_mip, mask = wr_mask & delegable_ints & ~env->miclaim; + uint64_t old_mip, mask = wr_mask & delegable_ints; uint32_t gin; + if (mask & MIP_SEIP) { + env->software_seip = new_val & MIP_SEIP; + new_val |= env->external_seip * MIP_SEIP; + } + if (mask) { old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask)); } else { |