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author | Jamin Lin <jamin_lin@aspeedtech.com> | 2024-06-04 13:44:34 +0800 |
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committer | Cédric Le Goater <clg@redhat.com> | 2024-06-16 21:08:54 +0200 |
commit | 5dd883ab0635c9f715c77cc32622e458a0724581 (patch) | |
tree | a0833fa698843f60b6bf7e1610f3d9c424074bdf /version.rc | |
parent | d831c5fd868225882c5297b34a241929c267be13 (diff) | |
download | qemu-5dd883ab0635c9f715c77cc32622e458a0724581.zip qemu-5dd883ab0635c9f715c77cc32622e458a0724581.tar.gz qemu-5dd883ab0635c9f715c77cc32622e458a0724581.tar.bz2 |
aspeed/soc: Add AST2700 support
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize handlers.
AST2700 is a 64 bits quad core cpus and support 8 watchdog.
Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to 8.
In addition, update AspeedSocState to support scuio, sli, sliio and intc.
Add TYPE_ASPEED27X0_SOC machine type.
The SDMC controller is unlocked at SPL stage.
At present, only supports to emulate booting
start from u-boot stage. Set SDMC controller
unlocked by default.
In INTC, each interrupt of INT 128 to INT 136 combines 32 interrupts.
It connect GICINT IRQ GPIO-OUTPUT pins to GIC device with irq 128 to 136.
And, if a device irq is 128 to 136, its irq GPIO-OUTPUT pin is connected to
GICINT or-gates instead of GIC device.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'version.rc')
0 files changed, 0 insertions, 0 deletions