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| author | Pranith Kumar <bobby.prani@gmail.com> | 2017-06-30 11:39:46 -0400 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-07-09 21:10:23 -1000 |
| commit | 2ae96c157ab3155baf6595c08cf5d3fe3c023a60 (patch) | |
| tree | 07a47caef81fb50fea0e1d4cab1ecc1b8cd07fec /util | |
| parent | 2acee8b2b5e6bba2935bb6ce5be92d0f0f9799cb (diff) | |
| download | qemu-2ae96c157ab3155baf6595c08cf5d3fe3c023a60.zip qemu-2ae96c157ab3155baf6595c08cf5d3fe3c023a60.tar.gz qemu-2ae96c157ab3155baf6595c08cf5d3fe3c023a60.tar.bz2 | |
util/cacheinfo: Fix warning generated by clang
Clang generates the following warning on aarch64 host:
CC util/cacheinfo.o
/home/pranith/qemu/util/cacheinfo.c:121:48: warning: value size does not match register size specified by the constraint and modifier [-Wasm-operand-widths]
asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
^
/home/pranith/qemu/util/cacheinfo.c:121:28: note: use constraint modifier "w"
asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
^~
%w0
Constraint modifier 'w' is not (yet?) accepted by gcc. Fix this by increasing the ctr size.
Tested-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Message-Id: <20170630153946.11997-1-bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'util')
| -rw-r--r-- | util/cacheinfo.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/util/cacheinfo.c b/util/cacheinfo.c index f987522..6253049 100644 --- a/util/cacheinfo.c +++ b/util/cacheinfo.c @@ -112,7 +112,7 @@ static void sys_cache_info(int *isize, int *dsize) static void arch_cache_info(int *isize, int *dsize) { if (*isize == 0 || *dsize == 0) { - unsigned ctr; + unsigned long ctr; /* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1, but (at least under Linux) these are marked protected by the |