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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-02-14 17:51:12 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-21 16:07:01 +0000 |
| commit | 62d96ff48510f4bf648ad12f5d3a5507227b026f (patch) | |
| tree | da22f0a73a142feb3004de737b575a1a11c9c80f /util/qemu-option.c | |
| parent | a1ed04dd79aabb9dbeeb5fa7d49f1a3de0357553 (diff) | |
| download | qemu-62d96ff48510f4bf648ad12f5d3a5507227b026f.zip qemu-62d96ff48510f4bf648ad12f5d3a5507227b026f.tar.gz qemu-62d96ff48510f4bf648ad12f5d3a5507227b026f.tar.bz2 | |
target/arm: Correct handling of PMCR_EL0.LC bit
The LC bit in the PMCR_EL0 register is supposed to be:
* read/write
* RES1 on an AArch64-only implementation
* an architecturally UNKNOWN value on reset
(and use of LC==0 by software is deprecated).
We were implementing it incorrectly as read-only always zero,
though we do have all the code needed to test it and behave
accordingly.
Instead make it a read-write bit which resets to 1 always, which
satisfies all the architectural requirements above.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200214175116.9164-18-peter.maydell@linaro.org
Diffstat (limited to 'util/qemu-option.c')
0 files changed, 0 insertions, 0 deletions