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| author | Fabiano Rosas <farosas@linux.ibm.com> | 2022-02-09 09:08:56 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-02-09 09:08:56 +0100 |
| commit | fe4b5c4c335c874ab05f3bdf40f2b62641d81c72 (patch) | |
| tree | 1ffcf328f87c1d80ae236dc5dff6d351946e1ebc /ui/sdl2.c | |
| parent | 7df40c5414b2f5e213fa30005f1600a429660cc5 (diff) | |
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target/ppc: 7xx: Set SRRs directly in exception code
The 7xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-11-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'ui/sdl2.c')
0 files changed, 0 insertions, 0 deletions