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authorMichael Clark <mjc@sifive.com>2018-12-14 00:19:03 +0000
committerPalmer Dabbelt <palmer@sifive.com>2018-12-20 12:08:43 -0800
commit194eef09d06358ea50b52340df853e9beeccce15 (patch)
tree454ffa1f0ac31beeb466ac5426deebb6a38dda98 /ui/input-linux.c
parente41848e5c9245947c09fb0cf3e160ec9350907f4 (diff)
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RISC-V: Enable second UART on sifive_e and sifive_u
Previously the second UARTs on the sifive_e and sifive_u machines where disabled due to check-qtest-riscv32 and check-qtest-riscv64 failures. Recent changes in the QEMU core serial code have resolved these failures so the second UARTs can be instantiated. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'ui/input-linux.c')
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