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| author | Mike Nawrocki <michael.nawrocki@gtri.gatech.edu> | 2021-02-03 11:55:52 -0500 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-02-11 11:50:13 +0000 |
| commit | 10d0ef3e6cfe228df4b2d3e27325f1b0e2b71fd5 (patch) | |
| tree | 409a37c68cd4d05d769b8fba6da5e6e26477b313 /trace-events | |
| parent | af903caed9fc62cc60a589da75e61ea8008c8265 (diff) | |
| download | qemu-10d0ef3e6cfe228df4b2d3e27325f1b0e2b71fd5.zip qemu-10d0ef3e6cfe228df4b2d3e27325f1b0e2b71fd5.tar.gz qemu-10d0ef3e6cfe228df4b2d3e27325f1b0e2b71fd5.tar.bz2 | |
target/arm: Fix SCR RES1 handling
The FW and AW bits of SCR_EL3 are RES1 only in some contexts. Force them
to 1 only when there is no support for AArch32 at EL1 or above.
The reset value will be 0x30 only if the CPU is AArch64-only; if there
is support for AArch32 at EL1 or above, it will be reset to 0.
Also adds helper function isar_feature_aa64_aa32_el1 to check if AArch32
is supported at EL1 or above.
Signed-off-by: Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210203165552.16306-2-michael.nawrocki@gtri.gatech.edu
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'trace-events')
0 files changed, 0 insertions, 0 deletions