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| author | Cédric Le Goater <clg@kaod.org> | 2019-09-04 09:05:01 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-09-13 16:05:01 +0100 |
| commit | c4e1f0b48322a9bc98c37f8413553cb6131daafe (patch) | |
| tree | 20da26dc3f7afd9678620282d69f2c736f7de00d /thunk.c | |
| parent | 811a5b1d6c2192cb9092040231dab173758bcca7 (diff) | |
| download | qemu-c4e1f0b48322a9bc98c37f8413553cb6131daafe.zip qemu-c4e1f0b48322a9bc98c37f8413553cb6131daafe.tar.gz qemu-c4e1f0b48322a9bc98c37f8413553cb6131daafe.tar.bz2 | |
aspeed/smc: Add support for DMAs
The FMC controller on the Aspeed SoCs support DMA to access the flash
modules. It can operate in a normal mode, to copy to or from the flash
module mapping window, or in a checksum calculation mode, to evaluate
the best clock settings for reads.
The model introduces two custom address spaces for DMAs: one for the
AHB window of the FMC flash devices and one for the DRAM. The latter
is populated using a "dram" link set from the machine with the RAM
container region.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190904070506.1052-6-clg@kaod.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'thunk.c')
0 files changed, 0 insertions, 0 deletions