Merge remote-tracking branch 'remotes/xtensa/tags/20180918-xtensa' into staging

target/xtensa updates:

- fix gdbstub register counts;
- add big-endian core test_kc705_be;
- convert to do_transaction_failed and add test for failed memory
  transactions;
- fix couple FPU2000 bugs;
- fix s32c1i implementation;
- clean up exception handlers generation in xtensa tests;
- add support for semihosting console input through a chardev.

# gpg: Signature made Tue 18 Sep 2018 18:35:50 BST
# gpg:                using RSA key 51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <filippov@cadence.com>"
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>"
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20180918-xtensa:
  target/xtensa: support input from chardev console
  target/xtensa: fix s32c1i TCGMemOp flags
  tests/tcg/xtensa: only generate defined exception handlers
  tests/tcg/xtensa: move exception handlers to separate section
  target/xtensa: fix FPU2000 bugs
  tests/tcg/xtensa: add test for failed memory transactions
  target/xtensa: convert to do_transaction_failed
  target/xtensa: add test_kc705_be core
  target/xtensa: clean up gdbstub register handling
  target/xtensa: fix gdbstub register counts

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

4 files changed, 163 insertions, 15 deletions

diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile
index 091518c..2f5691f 100644
--- a/tests/tcg/xtensa/Makefile
+++ b/tests/tcg/xtensa/Makefile
@@ -44,6 +44,7 @@ TESTCASES += test_mmu.tst
 TESTCASES += test_mul16.tst
 TESTCASES += test_mul32.tst
 TESTCASES += test_nsa.tst
+TESTCASES += test_phys_mem.tst
 ifdef XT
 TESTCASES += test_pipeline.tst
 endif
diff --git a/tests/tcg/xtensa/linker.ld.S b/tests/tcg/xtensa/linker.ld.S
index 5902302..d0f3315 100644
--- a/tests/tcg/xtensa/linker.ld.S
+++ b/tests/tcg/xtensa/linker.ld.S
@@ -24,64 +24,71 @@ SECTIONS
 
     .vector :
     {
+#if XCHAL_HAVE_WINDOWED
     . = XCHAL_WINDOW_OF4_VECOFS;
         *(.vector.window_overflow_4)
-        *(.vector.window_overflow_4.*)
     . = XCHAL_WINDOW_UF4_VECOFS;
         *(.vector.window_underflow_4)
-        *(.vector.window_underflow_4.*)
     . = XCHAL_WINDOW_OF8_VECOFS;
         *(.vector.window_overflow_8)
-        *(.vector.window_overflow_8.*)
     . = XCHAL_WINDOW_UF8_VECOFS;
         *(.vector.window_underflow_8)
-        *(.vector.window_underflow_8.*)
     . = XCHAL_WINDOW_OF12_VECOFS;
         *(.vector.window_overflow_12)
-        *(.vector.window_overflow_12.*)
     . = XCHAL_WINDOW_UF12_VECOFS;
         *(.vector.window_underflow_12)
-        *(.vector.window_underflow_12.*)
-
+#endif
 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
     . = XCHAL_INTLEVEL2_VECOFS;
         *(.vector.level2)
-        *(.vector.level2.*)
 #endif
 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3
     . = XCHAL_INTLEVEL3_VECOFS;
         *(.vector.level3)
-        *(.vector.level3.*)
 #endif
 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4
     . = XCHAL_INTLEVEL4_VECOFS;
         *(.vector.level4)
-        *(.vector.level4.*)
 #endif
 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5
     . = XCHAL_INTLEVEL5_VECOFS;
         *(.vector.level5)
-        *(.vector.level5.*)
 #endif
 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6
     . = XCHAL_INTLEVEL6_VECOFS;
         *(.vector.level6)
-        *(.vector.level6.*)
 #endif
 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7
     . = XCHAL_INTLEVEL7_VECOFS;
         *(.vector.level7)
-        *(.vector.level7.*)
 #endif
 
     . = XCHAL_KERNEL_VECOFS;
         *(.vector.kernel)
-        *(.vector.kernel.*)
     . = XCHAL_USER_VECOFS;
         *(.vector.user)
-        *(.vector.user.*)
     . = XCHAL_DOUBLEEXC_VECOFS;
         *(.vector.double)
+    } > ram
+
+    .vector.text :
+    {
+        *(.vector.window_overflow_4.*)
+        *(.vector.window_underflow_4.*)
+        *(.vector.window_overflow_8.*)
+        *(.vector.window_underflow_8.*)
+        *(.vector.window_overflow_12.*)
+        *(.vector.window_underflow_12.*)
+
+        *(.vector.level2.*)
+        *(.vector.level3.*)
+        *(.vector.level4.*)
+        *(.vector.level5.*)
+        *(.vector.level6.*)
+        *(.vector.level7.*)
+
+        *(.vector.kernel.*)
+        *(.vector.user.*)
         *(.vector.double.*)
     } > ram
 
diff --git a/tests/tcg/xtensa/test_phys_mem.S b/tests/tcg/xtensa/test_phys_mem.S
new file mode 100644
index 0000000..aae0a79
--- /dev/null
+++ b/tests/tcg/xtensa/test_phys_mem.S
@@ -0,0 +1,124 @@
+#include "macros.inc"
+
+test_suite phys_mem
+
+.purgem test_init
+
+.macro test_init
+    movi    a2, 0xc0000003 /* PPN */
+    movi    a3, 0xc0000004 /* VPN */
+    wdtlb   a2, a3
+    witlb   a2, a3
+    movi    a2, 0xc0000000
+    wsr     a2, ptevaddr
+.endm
+
+test inst_fetch_get_pte_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0x20000000
+    jx      a2
+2:
+    movi    a2, 0x20000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 16
+    assert  eq, a2, a3
+test_end
+
+test read_get_pte_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0x20000000
+1:
+    l32i    a3, a2, 0
+    test_fail
+2:
+    movi    a2, 0x20000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    movi    a2, 1b
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 24
+    assert  eq, a2, a3
+test_end
+
+test write_get_pte_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0x20000000
+1:
+    s32i    a3, a2, 0
+    test_fail
+2:
+    movi    a2, 0x20000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    movi    a2, 1b
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 24
+    assert  eq, a2, a3
+test_end
+
+test inst_fetch_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0xc0000000
+    jx      a2
+2:
+    movi    a2, 0xc0000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 14
+    assert  eq, a2, a3
+test_end
+
+test read_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0xc0000000
+1:
+    l32i    a3, a2, 0
+    test_fail
+2:
+    movi    a2, 0xc0000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    movi    a2, 1b
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 15
+    assert  eq, a2, a3
+test_end
+
+test write_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0xc0000000
+1:
+    s32i    a3, a2, 0
+    test_fail
+2:
+    movi    a2, 0xc0000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    movi    a2, 1b
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 15
+    assert  eq, a2, a3
+test_end
+
+test_suite_end
diff --git a/tests/tcg/xtensa/vectors.S b/tests/tcg/xtensa/vectors.S
index 265a181..6a9cb3c 100644
--- a/tests/tcg/xtensa/vectors.S
+++ b/tests/tcg/xtensa/vectors.S
@@ -1,3 +1,5 @@
+#include "core-isa.h"
+
 .macro vector name
 
 .section .vector.\name
@@ -20,19 +22,33 @@ handler_\name\(): .word 0
 
 .endm
 
+#if XCHAL_HAVE_WINDOWED
 vector window_overflow_4
 vector window_overflow_8
 vector window_overflow_12
 vector window_underflow_4
 vector window_underflow_8
 vector window_underflow_12
+#endif
 
+#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
 vector level2
+#endif
+#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3
 vector level3
+#endif
+#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4
 vector level4
+#endif
+#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5
 vector level5
+#endif
+#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6
 vector level6
+#endif
+#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7
 vector level7
+#endif
 
 vector kernel
 vector user