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authorPeter Maydell <peter.maydell@linaro.org>2018-11-02 17:17:12 +0000
committerPeter Maydell <peter.maydell@linaro.org>2018-11-02 17:17:12 +0000
commit7d56239f159afc2e7bd42623947e56ba48f37836 (patch)
treea03f541f1d8428df86d971981e1bde3fd263a493 /tests
parent69e2d03843412b9c076515b3aa9a71db161b6a1a (diff)
parent6f16da53ffe4567c0353f85055df04860eb4e6fc (diff)
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20181102' into staging
target-arm queue: * microbit: Add the UART to our nRF51 SoC model * Add a virtual Xilinx Versal board "xlnx-versal-virt" * hw/arm/virt: Set VIRT_COMPAT_3_0 compat * MAINTAINERS: Remove bouncing email in ARM ACPI * strongarm: mask off high[31:28] bits from dir and state registers * target/arm: Conditionalize some asserts on aarch32 support * hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro # gpg: Signature made Fri 02 Nov 2018 17:14:43 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20181102: hw/arm: versal: Add a virtual Xilinx Versal board hw/arm: versal: Add a model of Xilinx Versal SoC target/arm: Conditionalize some asserts on aarch32 support hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro strongarm: mask off high[31:28] bits from dir and state registers MAINTAINERS: Remove bouncing email in ARM ACPI tests/boot-serial-test: Add microbit board testcase hw/arm/nrf51_soc: Connect UART to nRF51 SoC hw/char: Implement nRF51 SoC UART hw/arm/virt: Set VIRT_COMPAT_3_0 compat Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests')
-rw-r--r--tests/boot-serial-test.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
index f865822..8ec6aed 100644
--- a/tests/boot-serial-test.c
+++ b/tests/boot-serial-test.c
@@ -62,6 +62,24 @@ static const uint8_t kernel_aarch64[] = {
0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */
};
+static const uint8_t kernel_nrf51[] = {
+ 0x00, 0x00, 0x00, 0x00, /* Stack top address */
+ 0x09, 0x00, 0x00, 0x00, /* Reset handler address */
+ 0x04, 0x4a, /* ldr r2, [pc, #16] Get ENABLE */
+ 0x04, 0x21, /* movs r1, #4 */
+ 0x11, 0x60, /* str r1, [r2] */
+ 0x04, 0x4a, /* ldr r2, [pc, #16] Get STARTTX */
+ 0x01, 0x21, /* movs r1, #1 */
+ 0x11, 0x60, /* str r1, [r2] */
+ 0x03, 0x4a, /* ldr r2, [pc, #12] Get TXD */
+ 0x54, 0x21, /* movs r1, 'T' */
+ 0x11, 0x60, /* str r1, [r2] */
+ 0xfe, 0xe7, /* b . */
+ 0x00, 0x25, 0x00, 0x40, /* 0x40002500 = UART ENABLE */
+ 0x08, 0x20, 0x00, 0x40, /* 0x40002008 = UART STARTTX */
+ 0x1c, 0x25, 0x00, 0x40 /* 0x4000251c = UART TXD */
+};
+
typedef struct testdef {
const char *arch; /* Target architecture */
const char *machine; /* Name of the machine */
@@ -105,6 +123,7 @@ static testdef_t tests[] = {
{ "hppa", "hppa", "", "SeaBIOS wants SYSTEM HALT" },
{ "aarch64", "virt", "-cpu cortex-a57", "TT", sizeof(kernel_aarch64),
kernel_aarch64 },
+ { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
{ NULL }
};