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authorBastian Koppelmann <kbastian@mail.uni-paderborn.de>2023-05-26 08:19:42 +0200
committerBastian Koppelmann <kbastian@mail.uni-paderborn.de>2023-06-07 18:20:40 +0200
commit2b8e2992c3c9aa6bee3dd23e2137a0923f7dc0aa (patch)
tree59dc151c51b7cfc4f1b8cef7473ba8646b9f870d /tests
parent8b50d564bee4d0e3864456ac8e92f981dba7959a (diff)
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tests/tcg/tricore: Uses label for memory addresses
the linker might rearrange sections, so lets reference memory by label name instead of addr + off. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230526061946.54514-3-kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'tests')
-rw-r--r--tests/tcg/tricore/asm/macros.h1
-rw-r--r--tests/tcg/tricore/asm/test_ld_bu.S4
-rw-r--r--tests/tcg/tricore/asm/test_ld_h.S8
3 files changed, 6 insertions, 7 deletions
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 3df2e0d..b5087b5 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -25,7 +25,6 @@
#define AREG_ADDR %a0
#define AREG_CORRECT_RESULT %a3
-#define MEM_BASE_ADDR 0xd0000000
#define DREG_DEV_ADDR %a15
diff --git a/tests/tcg/tricore/asm/test_ld_bu.S b/tests/tcg/tricore/asm/test_ld_bu.S
index ff9dac1..4a1f40c 100644
--- a/tests/tcg/tricore/asm/test_ld_bu.S
+++ b/tests/tcg/tricore/asm/test_ld_bu.S
@@ -9,7 +9,7 @@ _start:
# expect. addr reg val after load
# insn num expect. load value | pattern for loading
# | | | | |
- TEST_LD(ld.bu, 1, 0xff, MEM_BASE_ADDR + 4, [+AREG_ADDR]4) # pre_inc
- TEST_LD(ld.bu, 2, 0xad, MEM_BASE_ADDR + 4, [AREG_ADDR+]4) # post_inc
+ TEST_LD(ld.bu, 1, 0xff, test_data + 4, [+AREG_ADDR]4) # pre_inc
+ TEST_LD(ld.bu, 2, 0xad, test_data + 4, [AREG_ADDR+]4) # post_inc
TEST_PASSFAIL
diff --git a/tests/tcg/tricore/asm/test_ld_h.S b/tests/tcg/tricore/asm/test_ld_h.S
index d3c157a..f5e4959 100644
--- a/tests/tcg/tricore/asm/test_ld_h.S
+++ b/tests/tcg/tricore/asm/test_ld_h.S
@@ -7,9 +7,9 @@ test_data:
.global _start
_start:
# expect. addr reg val after load
-# insn num expect. load value | pattern for loading
-# | | | | |
- TEST_LD (ld.h, 1, 0xffffaffe, MEM_BASE_ADDR, [AREG_ADDR]2)
- TEST_LD_SRO(ld.h, 2, 0x000022ff, MEM_BASE_ADDR, [AREG_ADDR]4)
+# insn num expect. load value | pattern for loading
+# | | | | |
+ TEST_LD (ld.h, 1, 0xffffaffe, test_data, [AREG_ADDR]2)
+ TEST_LD_SRO(ld.h, 2, 0x000022ff, test_data, [AREG_ADDR]4)
TEST_PASSFAIL