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authorRichard Henderson <richard.henderson@linaro.org>2023-05-25 11:11:52 -0700
committerRichard Henderson <richard.henderson@linaro.org>2023-05-25 11:11:52 -0700
commita3cb6d5004ff638aefe686ecd540718a793bd1b1 (patch)
tree02b671fac114b157b5d9fcc75f0a8ce8aadd6789 /tests/docker
parent6ad2c71c238183437c91bb9fa0c8d87a9559eca3 (diff)
parenta30498fcea5a8b9c544324ccfb0186090104b229 (diff)
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Merge tag 'pull-tcg-20230525' of https://gitlab.com/rth7680/qemu into staging
tcg/mips: - Constant formation improvements - Replace MIPS_BE with HOST_BIG_ENDIAN - General cleanups tcg/riscv: - Improve setcond - Support movcond - Support Zbb, Zba # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmRvo9kdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/ECwf/eQSKdXsppLfgH1zj # 1VYOfSHB7kKacm5s9de6n0n0aT5DdBYGT1VkYqczMyanpYrK5jHIyzxYIcxa2KjN # /pMRKALUTq1Aku1wvovpybUT9Qt38+6jHw0U9inj11NJIYX4bheVJon3gztOUBRp # O67Z22RdfBBu+jL6VD00AE8OhCfeU7CZ+Bj9oNRKYCxXyr1ASla9gfTDy8UG+h2k # WqNti04xmgXqOZ+pEQ+ZyOCzhCHNLm8XBCtFjWXBe30ibX1PwWdSXqkuUtddd5nJ # MEbzQV42RCk1CNRrFz0RoAJhpcOEiSeDcI3Vx/PN8xS5mIS2jaWqW+5sMyCcI54h # JcfcUg== # =GI+F # -----END PGP SIGNATURE----- # gpg: Signature made Thu 25 May 2023 11:07:21 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-tcg-20230525' of https://gitlab.com/rth7680/qemu: (23 commits) tcg/riscv: Support CTZ, CLZ from Zbb tcg/riscv: Implement movcond tcg/riscv: Improve setcond expansion tcg/riscv: Support CPOP from Zbb tcg/riscv: Support REV8 from Zbb tcg/riscv: Support rotates from Zbb tcg/riscv: Use ADD.UW for guest address generation tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb tcg/riscv: Support ANDN, ORN, XNOR from Zbb tcg/riscv: Probe for Zba, Zbb, Zicond extensions disas/riscv: Decode czero.{eqz,nez} tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN tcg/mips: Use qemu_build_not_reached for LO/HI_OFF tcg/mips: Try three insns with shift and add in tcg_out_movi tcg/mips: Try tb-relative addresses in tcg_out_movi tcg/mips: Aggressively use the constant pool for n64 calls tcg/mips: Use the constant pool for 64-bit constants tcg/mips: Split out tcg_out_movi_two tcg/mips: Split out tcg_out_movi_one tcg/mips: Create and use TCG_REG_TB ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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