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authorRichard Henderson <richard.henderson@linaro.org>2023-04-23 20:10:00 +0100
committerRichard Henderson <richard.henderson@linaro.org>2023-05-05 17:21:03 +0100
commite3867bad0daca67df7e6312234bab6e20d4a7ae6 (patch)
tree7445a2eeb437796fd510a430ca3b9a437aff8481 /tcg
parent6073988eef3b23f27a06bef5d74bf138550f6df6 (diff)
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tcg/ppc: Introduce HostAddress
Collect the parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st} to use it. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg')
-rw-r--r--tcg/ppc/tcg-target.c.inc90
1 files changed, 47 insertions, 43 deletions
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index d1aa2a9..cd473de 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -2287,67 +2287,71 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
return tcg_out_fail_alignment(s, l);
}
-
#endif /* SOFTMMU */
+typedef struct {
+ TCGReg base;
+ TCGReg index;
+} HostAddress;
+
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addrhi,
MemOpIdx oi, TCGType data_type)
{
MemOp opc = get_memop(oi);
MemOp s_bits = opc & MO_SIZE;
- TCGReg rbase;
+ HostAddress h;
#ifdef CONFIG_SOFTMMU
tcg_insn_unit *label_ptr;
- addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), true);
+ h.index = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), true);
+ h.base = TCG_REG_R3;
/* Load a pointer into the current opcode w/conditional branch-link. */
label_ptr = s->code_ptr;
tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
-
- rbase = TCG_REG_R3;
#else /* !CONFIG_SOFTMMU */
unsigned a_bits = get_alignment_bits(opc);
if (a_bits) {
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
}
- rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
+ h.base = guest_base ? TCG_GUEST_BASE_REG : 0;
+ h.index = addrlo;
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
- addrlo = TCG_REG_TMP1;
+ h.index = TCG_REG_TMP1;
}
#endif
if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
if (opc & MO_BSWAP) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
- tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
- tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
- } else if (rbase != 0) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
- tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
- tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
- } else if (addrlo == datahi) {
- tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
- tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
+ tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index));
+ tcg_out32(s, LWBRX | TAB(datahi, h.base, TCG_REG_R0));
+ } else if (h.base != 0) {
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
+ tcg_out32(s, LWZX | TAB(datahi, h.base, h.index));
+ tcg_out32(s, LWZX | TAB(datalo, h.base, TCG_REG_R0));
+ } else if (h.index == datahi) {
+ tcg_out32(s, LWZ | TAI(datalo, h.index, 4));
+ tcg_out32(s, LWZ | TAI(datahi, h.index, 0));
} else {
- tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
- tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
+ tcg_out32(s, LWZ | TAI(datahi, h.index, 0));
+ tcg_out32(s, LWZ | TAI(datalo, h.index, 4));
}
} else {
uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
if (!have_isa_2_06 && insn == LDBRX) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
- tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
- tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
+ tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index));
+ tcg_out32(s, LWBRX | TAB(TCG_REG_R0, h.base, TCG_REG_R0));
tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
} else if (insn) {
- tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
+ tcg_out32(s, insn | TAB(datalo, h.base, h.index));
} else {
insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
- tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
+ tcg_out32(s, insn | TAB(datalo, h.base, h.index));
tcg_out_movext(s, TCG_TYPE_REG, datalo,
TCG_TYPE_REG, opc & MO_SSIZE, datalo);
}
@@ -2365,52 +2369,52 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
{
MemOp opc = get_memop(oi);
MemOp s_bits = opc & MO_SIZE;
- TCGReg rbase;
+ HostAddress h;
#ifdef CONFIG_SOFTMMU
tcg_insn_unit *label_ptr;
- addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), false);
+ h.index = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), false);
+ h.base = TCG_REG_R3;
/* Load a pointer into the current opcode w/conditional branch-link. */
label_ptr = s->code_ptr;
tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
-
- rbase = TCG_REG_R3;
#else /* !CONFIG_SOFTMMU */
unsigned a_bits = get_alignment_bits(opc);
if (a_bits) {
tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
}
- rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
+ h.base = guest_base ? TCG_GUEST_BASE_REG : 0;
+ h.index = addrlo;
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
- addrlo = TCG_REG_TMP1;
+ h.index = TCG_REG_TMP1;
}
#endif
if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
if (opc & MO_BSWAP) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
- tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
- tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
- } else if (rbase != 0) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
- tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
- tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
+ tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index));
+ tcg_out32(s, STWBRX | SAB(datahi, h.base, TCG_REG_R0));
+ } else if (h.base != 0) {
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
+ tcg_out32(s, STWX | SAB(datahi, h.base, h.index));
+ tcg_out32(s, STWX | SAB(datalo, h.base, TCG_REG_R0));
} else {
- tcg_out32(s, STW | TAI(datahi, addrlo, 0));
- tcg_out32(s, STW | TAI(datalo, addrlo, 4));
+ tcg_out32(s, STW | TAI(datahi, h.index, 0));
+ tcg_out32(s, STW | TAI(datalo, h.index, 4));
}
} else {
uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
if (!have_isa_2_06 && insn == STDBRX) {
- tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
- tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
+ tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index));
+ tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, h.index, 4));
tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
- tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
+ tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP1));
} else {
- tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
+ tcg_out32(s, insn | SAB(datalo, h.base, h.index));
}
}