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authorRichard Henderson <richard.henderson@linaro.org>2021-12-15 18:16:36 -0800
committerRichard Henderson <richard.henderson@linaro.org>2022-03-04 08:50:41 -1000
commitba597b66d998910b6d6192ee556f85e52004375d (patch)
tree753796eec56b2de6de21caaefe7cf276496b7d07 /tcg
parent21eab5bfaef49c6c0a8736943754e4e3a34a7139 (diff)
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tcg/i386: Detect AVX512
There are some operation sizes in some subsets of AVX512 that are missing from previous iterations of AVX. Detect them. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg')
-rw-r--r--tcg/i386/tcg-target.c.inc24
-rw-r--r--tcg/i386/tcg-target.h4
2 files changed, 26 insertions, 2 deletions
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index faa15ee..7516be5 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -171,6 +171,10 @@ bool have_bmi1;
bool have_popcnt;
bool have_avx1;
bool have_avx2;
+bool have_avx512bw;
+bool have_avx512dq;
+bool have_avx512vbmi2;
+bool have_avx512vl;
bool have_movbe;
#ifdef CONFIG_CPUID_H
@@ -3839,12 +3843,12 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
static void tcg_target_init(TCGContext *s)
{
#ifdef CONFIG_CPUID_H
- unsigned a, b, c, d, b7 = 0;
+ unsigned a, b, c, d, b7 = 0, c7 = 0;
unsigned max = __get_cpuid_max(0, 0);
if (max >= 7) {
/* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */
- __cpuid_count(7, 0, a, b7, c, d);
+ __cpuid_count(7, 0, a, b7, c7, d);
have_bmi1 = (b7 & bit_BMI) != 0;
have_bmi2 = (b7 & bit_BMI2) != 0;
}
@@ -3874,6 +3878,22 @@ static void tcg_target_init(TCGContext *s)
if ((xcrl & 6) == 6) {
have_avx1 = (c & bit_AVX) != 0;
have_avx2 = (b7 & bit_AVX2) != 0;
+
+ /*
+ * There are interesting instructions in AVX512, so long
+ * as we have AVX512VL, which indicates support for EVEX
+ * on sizes smaller than 512 bits. We are required to
+ * check that OPMASK and all extended ZMM state are enabled
+ * even if we're not using them -- the insns will fault.
+ */
+ if ((xcrl & 0xe0) == 0xe0
+ && (b7 & bit_AVX512F)
+ && (b7 & bit_AVX512VL)) {
+ have_avx512vl = true;
+ have_avx512bw = (b7 & bit_AVX512BW) != 0;
+ have_avx512dq = (b7 & bit_AVX512DQ) != 0;
+ have_avx512vbmi2 = (c7 & bit_AVX512VBMI2) != 0;
+ }
}
}
}
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index ecd0fa6..79af353 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -103,6 +103,10 @@ extern bool have_bmi1;
extern bool have_popcnt;
extern bool have_avx1;
extern bool have_avx2;
+extern bool have_avx512bw;
+extern bool have_avx512dq;
+extern bool have_avx512vbmi2;
+extern bool have_avx512vl;
extern bool have_movbe;
/* optional instructions */