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authorRichard Henderson <rth@twiddle.net>2015-02-20 11:13:50 -0800
committerRichard Henderson <rth@twiddle.net>2015-03-13 13:08:05 -0700
commit37ed3bf1ee07bb1a26adca0df8718f601f231c0b (patch)
tree051e8e211fb02d8ff2feead68df562859a4a3632 /tcg
parent51e3972c41598adc91fe3f4767057f5198dcc15c (diff)
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tcg: Complete handling of ALWAYS and NEVER
Missing from movcond, and brcondi_i32 (but not brcondi_i64). Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg')
-rw-r--r--tcg/tcg-op.c22
1 files changed, 17 insertions, 5 deletions
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 6674bb4..f7a2767 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -286,9 +286,13 @@ void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *l)
void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *l)
{
- TCGv_i32 t0 = tcg_const_i32(arg2);
- tcg_gen_brcond_i32(cond, arg1, t0, l);
- tcg_temp_free_i32(t0);
+ if (cond == TCG_COND_ALWAYS) {
+ tcg_gen_br(l);
+ } else if (cond != TCG_COND_NEVER) {
+ TCGv_i32 t0 = tcg_const_i32(arg2);
+ tcg_gen_brcond_i32(cond, arg1, t0, l);
+ tcg_temp_free_i32(t0);
+ }
}
void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
@@ -546,7 +550,11 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2)
{
- if (TCG_TARGET_HAS_movcond_i32) {
+ if (cond == TCG_COND_ALWAYS) {
+ tcg_gen_mov_i32(ret, v1);
+ } else if (cond == TCG_COND_NEVER) {
+ tcg_gen_mov_i32(ret, v2);
+ } else if (TCG_TARGET_HAS_movcond_i32) {
tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond);
} else {
TCGv_i32 t0 = tcg_temp_new_i32();
@@ -1590,7 +1598,11 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2)
{
- if (TCG_TARGET_REG_BITS == 32) {
+ if (cond == TCG_COND_ALWAYS) {
+ tcg_gen_mov_i64(ret, v1);
+ } else if (cond == TCG_COND_NEVER) {
+ tcg_gen_mov_i64(ret, v2);
+ } else if (TCG_TARGET_REG_BITS == 32) {
TCGv_i32 t0 = tcg_temp_new_i32();
TCGv_i32 t1 = tcg_temp_new_i32();
tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0,