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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-07-09 18:36:34 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-07-14 12:19:00 +0200 |
| commit | 1789d4274b851fb8fdf4a947ce5474c63e813d0d (patch) | |
| tree | 2ef884d0b1bdf440b5b317194c962293f1fbff00 /tcg | |
| parent | 80f4d7c3ae216c191fb403e149bcba88d6aa40bb (diff) | |
| download | qemu-1789d4274b851fb8fdf4a947ce5474c63e813d0d.zip qemu-1789d4274b851fb8fdf4a947ce5474c63e813d0d.tar.gz qemu-1789d4274b851fb8fdf4a947ce5474c63e813d0d.tar.bz2 | |
tcg/aarch64: Fix output of extract2 opcodes
This patch fixes two problems:
(1) The inputs to the EXTR insn were reversed,
(2) The input constraints use rZ, which means that we need to use
the REG0 macro in order to supply XZR for a constant 0 input.
Fixes: 464c2969d5d
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/aarch64/tcg-target.inc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index b0f8106..0713448 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -2226,7 +2226,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_extract2_i64: case INDEX_op_extract2_i32: - tcg_out_extr(s, ext, a0, a1, a2, args[3]); + tcg_out_extr(s, ext, a0, REG0(2), REG0(1), args[3]); break; case INDEX_op_add2_i32: |