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authorRichard Henderson <richard.henderson@linaro.org>2022-10-21 10:34:21 +1000
committerRichard Henderson <richard.henderson@linaro.org>2023-02-04 06:19:42 -1000
commit896c76e6ba5d9a3444fb8528fdc407747ecc82f2 (patch)
tree775801d8011510f2627a1ce32bf44d5e88e0d0ac /tcg/tci/tcg-target.h
parentc4f4a00ac7d947c9b100e3cb62755a9a157df1fa (diff)
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tcg/tci: Fix big-endian return register ordering
We expect the backend to require register pairs in host-endian ordering, thus for big-endian the first register of a pair contains the high part. We were forcing R0 to contain the low part for calls. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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