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authorRichard Henderson <richard.henderson@linaro.org>2020-12-09 13:58:39 -0600
committerRichard Henderson <richard.henderson@linaro.org>2021-01-07 05:09:06 -1000
commit07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1 (patch)
treea22f2b213b2cb96c8e0e30c69bca9edb00b678bc /tcg/tcg.c
parentd2ef1b83a7a2047e0e36d7b62b3a5d151ab958f5 (diff)
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tcg: Introduce INDEX_op_qemu_st8_i32
Enable this on i386 to restrict the set of input registers for an 8-bit store, as required by the architecture. This removes the last use of scratch registers for user-only mode. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tcg.c')
-rw-r--r--tcg/tcg.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/tcg/tcg.c b/tcg/tcg.c
index ebb9466..95aacc8 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1427,6 +1427,9 @@ bool tcg_op_supported(TCGOpcode op)
case INDEX_op_qemu_st_i64:
return true;
+ case INDEX_op_qemu_st8_i32:
+ return TCG_TARGET_HAS_qemu_st8_i32;
+
case INDEX_op_goto_ptr:
return TCG_TARGET_HAS_goto_ptr;
@@ -2087,6 +2090,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
break;
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_st_i32:
+ case INDEX_op_qemu_st8_i32:
case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_st_i64:
{