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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-08-28 19:33:30 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-09-01 11:19:32 +0100 |
| commit | 46a4b854525cb9f34a611f6ada6cdff1eab0ac2d (patch) | |
| tree | ed4928cfc83e2868883cc8570ca2e08ac3c4dbcc /tcg/sparc | |
| parent | f61e5c43b86907dea17f431b528d806659d62bcb (diff) | |
| download | qemu-46a4b854525cb9f34a611f6ada6cdff1eab0ac2d.zip qemu-46a4b854525cb9f34a611f6ada6cdff1eab0ac2d.tar.gz qemu-46a4b854525cb9f34a611f6ada6cdff1eab0ac2d.tar.bz2 | |
target/arm: Implement VFP fp16 VMOV between gp and halfprec registers
Implement the VFP fp16 variant of VMOV that transfers a 16-bit
value between a general purpose register and a VFP register.
Note that Rt == 15 is UNPREDICTABLE; since this insn is v8 and later
only we have no need to replicate the old "updates CPSR.NZCV"
behaviour that the singleprec version of this insn does.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-22-peter.maydell@linaro.org
Diffstat (limited to 'tcg/sparc')
0 files changed, 0 insertions, 0 deletions