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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-05-01 10:57:11 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-06-05 12:04:28 -0700 |
| commit | d46259c037e51fb6516199305fe8f0994df3d46e (patch) | |
| tree | 4a2cedcb5ce045685b565a0947f5dbb479556c07 /tcg/s390x | |
| parent | e5b490637708a688e303a51d47fea3bd14ec98f6 (diff) | |
| download | qemu-d46259c037e51fb6516199305fe8f0994df3d46e.zip qemu-d46259c037e51fb6516199305fe8f0994df3d46e.tar.gz qemu-d46259c037e51fb6516199305fe8f0994df3d46e.tar.bz2 | |
tcg: Split out tcg-target-reg-bits.h
Often, the only thing we need to know about the TCG host
is the register size.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/s390x')
| -rw-r--r-- | tcg/s390x/tcg-target-reg-bits.h | 17 | ||||
| -rw-r--r-- | tcg/s390x/tcg-target.c.inc | 5 |
2 files changed, 17 insertions, 5 deletions
diff --git a/tcg/s390x/tcg-target-reg-bits.h b/tcg/s390x/tcg-target-reg-bits.h new file mode 100644 index 0000000..b01414e --- /dev/null +++ b/tcg/s390x/tcg-target-reg-bits.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2009 Ulrich Hecht <uli@suse.de> + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +/* We only support generating code for 64-bit mode. */ +#if UINTPTR_MAX == UINT64_MAX +# define TCG_TARGET_REG_BITS 64 +#else +# error "unsupported code generation mode" +#endif + +#endif diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index aeddebb..a878acd 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -24,11 +24,6 @@ * THE SOFTWARE. */ -/* We only support generating code for 64-bit mode. */ -#if TCG_TARGET_REG_BITS != 64 -#error "unsupported code generation mode" -#endif - #include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" #include "elf.h" |