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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-10-12 20:45:36 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-10-22 16:32:28 -0700 |
| commit | cf0ed30eb10c7341fd1f253446e3bbb6e0114c30 (patch) | |
| tree | 626b173d640456d56b5dbfeb82d548924332af3c /tcg/riscv | |
| parent | 5b5bd4a9b1ddd724b5f12725fa186e75047dbfe1 (diff) | |
| download | qemu-cf0ed30eb10c7341fd1f253446e3bbb6e0114c30.zip qemu-cf0ed30eb10c7341fd1f253446e3bbb6e0114c30.tar.gz qemu-cf0ed30eb10c7341fd1f253446e3bbb6e0114c30.tar.bz2 | |
tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zero
Fixes: 92c041c59b ("tcg/riscv: Add the prologue generation and register the JIT")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/riscv')
| -rw-r--r-- | tcg/riscv/tcg-target.c.inc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d6dbcaf..dc71f82 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -2076,8 +2076,10 @@ static void tcg_target_qemu_prologue(TCGContext *s) } #if !defined(CONFIG_SOFTMMU) - tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); - tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); + if (guest_base) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); + } #endif /* Call generated code */ |