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authorRichard Henderson <richard.henderson@linaro.org>2023-04-05 18:30:56 -0700
committerRichard Henderson <richard.henderson@linaro.org>2023-04-23 08:24:07 +0100
commit9c6aa274a494ce807e998a3652fa16a3d2da4387 (patch)
treea003adcb20368ef57d7242bffd948ac29c452de4 /tcg/riscv
parent9ecf5f61b8f468f17483f325f565802c645983a5 (diff)
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tcg: Split out tcg_out_exts_i32_i64
We will need a backend interface for type extension with sign. Use it in tcg_reg_alloc_op in the meantime. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/riscv')
-rw-r--r--tcg/riscv/tcg-target.c.inc7
1 files changed, 6 insertions, 1 deletions
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 1d91fd1..7bd3b42 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -602,6 +602,11 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
}
+static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_ext32s(s, ret, arg);
+}
+
static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
TCGReg addr, intptr_t offset)
{
@@ -1602,7 +1607,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_extrl_i64_i32:
- case INDEX_op_ext_i32_i64:
tcg_out_ext32s(s, a0, a1);
break;
@@ -1639,6 +1643,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ext16u_i64:
case INDEX_op_ext32s_i64:
case INDEX_op_ext32u_i64:
+ case INDEX_op_ext_i32_i64:
default:
g_assert_not_reached();
}