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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-04-05 18:43:47 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-04-23 08:46:45 +0100 |
| commit | 3ea9be33400f14305565a9a094cb6031c07183d5 (patch) | |
| tree | 7c96b5cba009ec1ff6efd18d3977e86c7f0b17e6 /tcg/riscv | |
| parent | 4745b156b8412ef12af32bd474fee70c25940950 (diff) | |
| download | qemu-3ea9be33400f14305565a9a094cb6031c07183d5.zip qemu-3ea9be33400f14305565a9a094cb6031c07183d5.tar.gz qemu-3ea9be33400f14305565a9a094cb6031c07183d5.tar.bz2 | |
tcg/riscv: Conditionalize tcg_out_exts_i32_i64
Since TCG_TYPE_I32 values are kept sign-extended in registers, via "w"
instructions, we don't need to extend if the register matches.
This is already relied upon by comparisons.
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/riscv')
| -rw-r--r-- | tcg/riscv/tcg-target.c.inc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 328cbc0..266fe14 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -609,7 +609,9 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) { - tcg_out_ext32s(s, ret, arg); + if (ret != arg) { + tcg_out_ext32s(s, ret, arg); + } } static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) |