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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-11-07 10:42:56 +1100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-05-16 16:30:25 -0700 |
| commit | 12fde9bcdb52118495d10c32ed375679f23e323c (patch) | |
| tree | af2fc03fc6bf402cad84ec11be6799fd0a373f8f /tcg/riscv | |
| parent | 7b8801071951c55dc506c1fca8b40ba292a28d6e (diff) | |
| download | qemu-12fde9bcdb52118495d10c32ed375679f23e323c.zip qemu-12fde9bcdb52118495d10c32ed375679f23e323c.tar.gz qemu-12fde9bcdb52118495d10c32ed375679f23e323c.tar.bz2 | |
tcg: Add INDEX_op_qemu_{ld,st}_i128
Add opcodes for backend support for 128-bit memory operations.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/riscv')
| -rw-r--r-- | tcg/riscv/tcg-target.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index dece3b3..494c986 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -163,6 +163,8 @@ typedef enum { #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_NEED_LDST_LABELS |