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| author | Andrew Bresticker <abrestic@rivosinc.com> | 2022-12-15 17:45:41 -0500 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-01-20 10:14:14 +1000 |
| commit | e471a8c9850f1af0c1bc5768ca28285348cdd6c5 (patch) | |
| tree | a8be9f3c6190f5b4de4f52e97ac7b1a68e45e868 /tcg/riscv/tcg-target.c.inc | |
| parent | 06d85c24c28f42a57680dc21955e343f58d93089 (diff) | |
| download | qemu-e471a8c9850f1af0c1bc5768ca28285348cdd6c5.zip qemu-e471a8c9850f1af0c1bc5768ca28285348cdd6c5.tar.gz qemu-e471a8c9850f1af0c1bc5768ca28285348cdd6c5.tar.bz2 | |
target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1
Per the AIA specification, writes to stimecmp from VS level should
trap when hvictl.VTI is set since the write may cause vsip.STIP to
become unset.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp support")
Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221215224541.1423431-2-abrestic@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'tcg/riscv/tcg-target.c.inc')
0 files changed, 0 insertions, 0 deletions