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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-05-01 10:57:11 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-06-05 12:04:28 -0700 |
| commit | d46259c037e51fb6516199305fe8f0994df3d46e (patch) | |
| tree | 4a2cedcb5ce045685b565a0947f5dbb479556c07 /tcg/ppc | |
| parent | e5b490637708a688e303a51d47fea3bd14ec98f6 (diff) | |
| download | qemu-d46259c037e51fb6516199305fe8f0994df3d46e.zip qemu-d46259c037e51fb6516199305fe8f0994df3d46e.tar.gz qemu-d46259c037e51fb6516199305fe8f0994df3d46e.tar.bz2 | |
tcg: Split out tcg-target-reg-bits.h
Often, the only thing we need to know about the TCG host
is the register size.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/ppc')
| -rw-r--r-- | tcg/ppc/tcg-target-reg-bits.h | 16 | ||||
| -rw-r--r-- | tcg/ppc/tcg-target.h | 5 |
2 files changed, 16 insertions, 5 deletions
diff --git a/tcg/ppc/tcg-target-reg-bits.h b/tcg/ppc/tcg-target-reg-bits.h new file mode 100644 index 0000000..0efa80e --- /dev/null +++ b/tcg/ppc/tcg-target-reg-bits.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2008 Fabrice Bellard + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +#ifdef _ARCH_PPC64 +# define TCG_TARGET_REG_BITS 64 +#else +# define TCG_TARGET_REG_BITS 32 +#endif + +#endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 40f20b0..c7552b6 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -25,11 +25,6 @@ #ifndef PPC_TCG_TARGET_H #define PPC_TCG_TARGET_H -#ifdef _ARCH_PPC64 -# define TCG_TARGET_REG_BITS 64 -#else -# define TCG_TARGET_REG_BITS 32 -#endif #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) #define TCG_TARGET_NB_REGS 64 |