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| author | Richard Henderson <rth@twiddle.net> | 2017-07-31 22:02:31 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-09-07 11:57:34 -0700 |
| commit | a85833933628384d74ec412024d55cf012640287 (patch) | |
| tree | cd3ed9260f5c9813102ffce4c006e7bbf3419c03 /tcg/i386 | |
| parent | cda4a338c4243fa3bff4498b935340ac7121cc76 (diff) | |
| download | qemu-a85833933628384d74ec412024d55cf012640287.zip qemu-a85833933628384d74ec412024d55cf012640287.tar.gz qemu-a85833933628384d74ec412024d55cf012640287.tar.bz2 | |
tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h
Replace the USE_DIRECT_JUMP ifdef with a TCG_TARGET_HAS_direct_jump
boolean test. Replace the tb_set_jmp_target1 ifdef with an unconditional
function tb_target_set_jmp_target.
While we're touching all backends, add a parameter for tb->tc_ptr;
we're going to need it shortly for some backends.
Move tb_set_jmp_target and tb_add_jump from exec-all.h to cpu-exec.c.
This opens the possibility for TCG_TARGET_HAS_direct_jump to be
a runtime decision -- based on host cpu capabilities, the size of
code_gen_buffer, or a future debugging switch.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/i386')
| -rw-r--r-- | tcg/i386/tcg-target.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 73a15f7..2fd28fa 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -108,6 +108,7 @@ extern bool have_popcnt; #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_direct_jump 1 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_extrl_i64_i32 0 @@ -166,6 +167,14 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, + uintptr_t jmp_addr, uintptr_t addr) +{ + /* patch the branch destination */ + atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); + /* no need to flush icache explicitly */ +} + /* This defines the natural memory order supported by this * architecture before guarantees made by various barrier * instructions. |