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authorRichard Henderson <richard.henderson@linaro.org>2023-08-05 14:32:57 +0000
committerRichard Henderson <richard.henderson@linaro.org>2023-08-24 11:22:42 -0700
commitfe06b8973385c9421b2988239cadb9d091cdc628 (patch)
treebea69c350888034f0cdb1300bd164408711e0438 /tcg/arm
parentf58a7dea0f0652779e1525f072ef45bf99dbfd72 (diff)
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tcg/arm: Implement negsetcond_i32
Trivial, as we simply need to load a different constant in the conditional move. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/arm')
-rw-r--r--tcg/arm/tcg-target.c.inc9
-rw-r--r--tcg/arm/tcg-target.h2
2 files changed, 10 insertions, 1 deletions
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 83e2860..162df38 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1975,6 +1975,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
ARITH_MOV, args[0], 0, 0);
break;
+ case INDEX_op_negsetcond_i32:
+ tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
+ args[1], args[2], const_args[2]);
+ tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
+ ARITH_MVN, args[0], 0, 0);
+ tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
+ ARITH_MOV, args[0], 0, 0);
+ break;
case INDEX_op_brcond2_i32:
c = tcg_out_cmp2(s, args, const_args);
@@ -2112,6 +2120,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_add_i32:
case INDEX_op_sub_i32:
case INDEX_op_setcond_i32:
+ case INDEX_op_negsetcond_i32:
return C_O1_I2(r, r, rIN);
case INDEX_op_and_i32:
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index ad66f11..311a985 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -116,7 +116,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
#define TCG_TARGET_HAS_extract2_i32 1
#define TCG_TARGET_HAS_movcond_i32 1
-#define TCG_TARGET_HAS_negsetcond_i32 0
+#define TCG_TARGET_HAS_negsetcond_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
#define TCG_TARGET_HAS_muls2_i32 1
#define TCG_TARGET_HAS_muluh_i32 0