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| author | Aurelien Jarno <aurelien@aurel32.net> | 2010-03-20 12:10:20 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-03-20 12:10:20 +0100 |
| commit | 26c5d372e4848cbe85bcda10a4c5e98ad3aa051a (patch) | |
| tree | cecbf7c942a384e2d139c081ee4b8e66c1b7e6dc /tcg/arm | |
| parent | 30138f2814a3d2748937a32620eb4e68a3c58041 (diff) | |
| download | qemu-26c5d372e4848cbe85bcda10a4c5e98ad3aa051a.zip qemu-26c5d372e4848cbe85bcda10a4c5e98ad3aa051a.tar.gz qemu-26c5d372e4848cbe85bcda10a4c5e98ad3aa051a.tar.bz2 | |
tcg/arm: fix load/store definitions for 32-bit targets
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'tcg/arm')
| -rw-r--r-- | tcg/arm/tcg-target.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 35e14c1..b50bb76 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1580,6 +1580,19 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } }, { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } }, +#if TARGET_LONG_BITS == 32 + { INDEX_op_qemu_ld8u, { "r", "x" } }, + { INDEX_op_qemu_ld8s, { "r", "x" } }, + { INDEX_op_qemu_ld16u, { "r", "x" } }, + { INDEX_op_qemu_ld16s, { "r", "x" } }, + { INDEX_op_qemu_ld32u, { "r", "x" } }, + { INDEX_op_qemu_ld64, { "d", "r", "x" } }, + + { INDEX_op_qemu_st8, { "x", "x" } }, + { INDEX_op_qemu_st16, { "x", "x" } }, + { INDEX_op_qemu_st32, { "x", "x" } }, + { INDEX_op_qemu_st64, { "x", "D", "x" } }, +#else { INDEX_op_qemu_ld8u, { "r", "x", "X" } }, { INDEX_op_qemu_ld8s, { "r", "x", "X" } }, { INDEX_op_qemu_ld16u, { "r", "x", "X" } }, @@ -1591,6 +1604,7 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_qemu_st16, { "x", "x", "X" } }, { INDEX_op_qemu_st32, { "x", "x", "X" } }, { INDEX_op_qemu_st64, { "x", "D", "x", "X" } }, +#endif { INDEX_op_ext8s_i32, { "r", "r" } }, { INDEX_op_ext16s_i32, { "r", "r" } }, |