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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-02-05 01:48:20 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-02-05 10:24:14 -1000 |
| commit | 2dfa2f18717f3294e8612637a60fc58576ef55b5 (patch) | |
| tree | 8285f701822051a3cb95b3a3d4c27cffac6087b7 /tcg/aarch64 | |
| parent | 37c8c531d61e34b69750aaeb61f7a0d5e9d9de3d (diff) | |
| download | qemu-2dfa2f18717f3294e8612637a60fc58576ef55b5.zip qemu-2dfa2f18717f3294e8612637a60fc58576ef55b5.tar.gz qemu-2dfa2f18717f3294e8612637a60fc58576ef55b5.tar.bz2 | |
tcg/aarch64: Do not convert TCGArg to temps that are not temps
Fixes INDEX_op_rotli_vec for aarch64 host, where the 3rd
argument is an integer, not a temporary, which now tickles
an assert added in e89b28a6350.
Previously, the value computed into v2 would be garbage for
rotli_vec, but as the value was unused it caused no harm.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/aarch64')
| -rw-r--r-- | tcg/aarch64/tcg-target.c.inc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 3c1ee39..1376cdc 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2488,7 +2488,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, v0 = temp_tcgv_vec(arg_temp(a0)); v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); a2 = va_arg(va, TCGArg); - v2 = temp_tcgv_vec(arg_temp(a2)); + va_end(va); switch (opc) { case INDEX_op_rotli_vec: @@ -2502,6 +2502,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: /* Right shifts are negative left shifts for AArch64. */ + v2 = temp_tcgv_vec(arg_temp(a2)); t1 = tcg_temp_new_vec(type); tcg_gen_neg_vec(vece, t1, v2); opc = (opc == INDEX_op_shrv_vec @@ -2512,6 +2513,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, break; case INDEX_op_rotlv_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); t1 = tcg_temp_new_vec(type); c1 = tcg_constant_vec(type, vece, 8 << vece); tcg_gen_sub_vec(vece, t1, v2, c1); @@ -2525,6 +2527,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, break; case INDEX_op_rotrv_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); t1 = tcg_temp_new_vec(type); t2 = tcg_temp_new_vec(type); c1 = tcg_constant_vec(type, vece, 8 << vece); @@ -2543,8 +2546,6 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, default: g_assert_not_reached(); } - - va_end(va); } static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) |