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authorMax Filippov <jcmvbkbc@gmail.com>2019-02-09 20:43:58 -0800
committerMax Filippov <jcmvbkbc@gmail.com>2019-02-18 21:29:08 -0800
commit0e7c887919e44f25491a4eb86403e947d9d54937 (patch)
tree266b0c66b28675598bc506415130c6deb1144839 /target/xtensa
parent2012f47e2371537bf41a9347af6db1d3d675a1a4 (diff)
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target/xtensa: move xtensa_finalize_config to xtensa_core_class_init
Don't run xtensa_finalize_config at the time of core registration, instead run it at the CPU class initialization. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa')
-rw-r--r--target/xtensa/cpu.h1
-rw-r--r--target/xtensa/helper.c36
-rw-r--r--target/xtensa/overlay_tool.h1
3 files changed, 19 insertions, 19 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index f186124..47d80a5 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -566,7 +566,6 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
void xtensa_translate_init(void);
void xtensa_breakpoint_handler(CPUState *cs);
-void xtensa_finalize_config(XtensaConfig *config);
void xtensa_register_core(XtensaConfigList *node);
void xtensa_sim_open_console(Chardev *chr);
void check_interrupts(CPUXtensaState *s);
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index 6cf1dbb..321ca42 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -34,22 +34,6 @@
static struct XtensaConfigList *xtensa_cores;
-static void xtensa_core_class_init(ObjectClass *oc, void *data)
-{
- CPUClass *cc = CPU_CLASS(oc);
- XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
- const XtensaConfig *config = data;
-
- xcc->config = config;
-
- /* Use num_core_regs to see only non-privileged registers in an unmodified
- * gdb. Use num_regs to see all registers. gdb modification is required
- * for that: reset bit 0 in the 'flags' field of the registers definitions
- * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
- */
- cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
-}
-
static void init_libisa(XtensaConfig *config)
{
unsigned i, j;
@@ -91,7 +75,7 @@ static void init_libisa(XtensaConfig *config)
config->a_regfile = xtensa_regfile_lookup(config->isa, "AR");
}
-void xtensa_finalize_config(XtensaConfig *config)
+static void xtensa_finalize_config(XtensaConfig *config)
{
if (config->isa_internal) {
init_libisa(config);
@@ -112,6 +96,24 @@ void xtensa_finalize_config(XtensaConfig *config)
}
}
+static void xtensa_core_class_init(ObjectClass *oc, void *data)
+{
+ CPUClass *cc = CPU_CLASS(oc);
+ XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
+ XtensaConfig *config = data;
+
+ xtensa_finalize_config(config);
+ xcc->config = config;
+
+ /*
+ * Use num_core_regs to see only non-privileged registers in an unmodified
+ * gdb. Use num_regs to see all registers. gdb modification is required
+ * for that: reset bit 0 in the 'flags' field of the registers definitions
+ * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
+ */
+ cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
+}
+
void xtensa_register_core(XtensaConfigList *node)
{
TypeInfo type = {
diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h
index 12609a0..ea07576 100644
--- a/target/xtensa/overlay_tool.h
+++ b/target/xtensa/overlay_tool.h
@@ -377,7 +377,6 @@
static XtensaConfigList node = { \
.config = &core, \
}; \
- xtensa_finalize_config(&core); \
xtensa_register_core(&node); \
}
#else