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authorRichard Henderson <richard.henderson@linaro.org>2019-04-03 07:46:30 +0700
committerRichard Henderson <richard.henderson@linaro.org>2019-05-10 11:12:50 -0700
commitb008c45612f652edb8cae8ec9620a3f57b2500e3 (patch)
tree83cdd2791256e2c798897545ba223148ed7d4ee7 /target/xtensa/cpu.h
parentc5d417da4a5be88e8da9523dcc38d2efc1898081 (diff)
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target/xtensa: Convert to CPUClass::tlb_fill
Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/xtensa/cpu.h')
-rw-r--r--target/xtensa/cpu.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 5d23e134..68d89f8 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -552,8 +552,9 @@ static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
#define ENV_OFFSET offsetof(XtensaCPU, env)
-int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size,
- int mmu_idx);
+bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
void xtensa_cpu_do_interrupt(CPUState *cpu);
bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,