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| author | Max Filippov <jcmvbkbc@gmail.com> | 2019-02-18 03:11:40 -0800 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2019-02-28 04:43:22 -0800 |
| commit | eb3f4298c96d79a5a67b904c28f293864cc5ccc3 (patch) | |
| tree | 5cb370d2454e556508d48b6cedbdf84a13558ff2 /target/xtensa/cpu.h | |
| parent | 068e538a54552289a58689f21c99ed3696e59961 (diff) | |
| download | qemu-eb3f4298c96d79a5a67b904c28f293864cc5ccc3.zip qemu-eb3f4298c96d79a5a67b904c28f293864cc5ccc3.tar.gz qemu-eb3f4298c96d79a5a67b904c28f293864cc5ccc3.tar.bz2 | |
target/xtensa: implement PREFCTL SR
Cache prefetch option adds an unprivileged SR PREFCTL. Add trivial
implementation for this SR.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/cpu.h')
| -rw-r--r-- | target/xtensa/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index a01a94e..4d81526 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -131,6 +131,7 @@ enum { ACCLO = 16, ACCHI = 17, MR = 32, + PREFCTL = 40, WINDOW_BASE = 72, WINDOW_START = 73, PTEVADDR = 83, |