From eb3f4298c96d79a5a67b904c28f293864cc5ccc3 Mon Sep 17 00:00:00 2001
From: Max Filippov <jcmvbkbc@gmail.com>
Date: Mon, 18 Feb 2019 03:11:40 -0800
Subject: target/xtensa: implement PREFCTL SR

Cache prefetch option adds an unprivileged SR PREFCTL. Add trivial
implementation for this SR.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
 target/xtensa/cpu.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'target/xtensa/cpu.h')

diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index a01a94e..4d81526 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -131,6 +131,7 @@ enum {
     ACCLO = 16,
     ACCHI = 17,
     MR = 32,
+    PREFCTL = 40,
     WINDOW_BASE = 72,
     WINDOW_START = 73,
     PTEVADDR = 83,
-- 
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