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authorFrédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>2022-01-06 22:00:51 +0100
committerAlistair Francis <alistair.francis@wdc.com>2022-01-08 15:46:10 +1000
commitfc313c64345453c7a668d765610dfd7135e21a98 (patch)
tree336a2b0e28691f2333931bf366f85e70e60f3091 /target/tricore
parentdfdb46a3765bdab40a0b36722b4828d52ea8de96 (diff)
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exec/memop: Adding signedness to quad definitions
Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/tricore')
-rw-r--r--target/tricore/translate.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 0708440..417edbd 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -246,7 +246,7 @@ static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
TCGv_i64 temp = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp, rl, rh);
- tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
+ tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ);
tcg_temp_free_i64(temp);
}
@@ -264,7 +264,7 @@ static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
{
TCGv_i64 temp = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
+ tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEUQ);
/* write back to two 32 bit regs */
tcg_gen_extr_i64_i32(rl, rh, temp);